公开(公告)号：US11502392B2

公开(公告)日：2022-11-15

申请号：US17108953

申请日：2020-12-01

Applicant: SJ Semiconductor (Jiangyin) Corporation

Inventor： Yenheng Chen ,  Chengchung Lin ,  Chengtar Wu ,  Jangshen Lin

IPC: H01L23/34 ,  H01Q1/22 ,  H01L23/66 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L21/683

Abstract: The present disclosure provides a packaging structure and a packaging method for an antenna. The packaging structure comprises a redistribution layer, having a first surface and an opposite second surface; a first metal joint pin, formed on the second surface of the redistribution layer; a first packaging layer, disposed on the redistribution layer covering the first metal joint pin; a first antenna metal layer, patterned on the first packaging layer, and a portion of the first antenna metal layer electrically connects with the first metal joint pin; a second metal joint pin, formed on the first antenna metal layer; a second packaging layer, disposed on the first antenna metal layer covering the second metal joint pin; a second antenna metal layer, formed on the second packaging layer; and a metal bump and an antenna circuit chip, bonded to the first surface of the redistribution layer.

公开(公告)号：US11121065B2

公开(公告)日：2021-09-14

申请号：US16232988

申请日：2018-12-26

Applicant: SJ Semiconductor (Jiangyin) Corporation

Inventor： Yenheng Chen ,  Chentar Wu ,  Chengchung Lin

IPC: H01L23/498 ,  H01L23/15 ,  H01L23/31 ,  H01L23/66

Abstract: The present application provides a semiconductor packaging structure with an antenna assembly, including: a substrate with through-substrate-via holes; a rewiring layer, located on the substrate; metal bumps, located on and electrically connected to the rewiring layer; a semiconductor chip, located on a surface of the rewiring layer and electrically connected to the rewiring layer; a conductive column, filling in the via hole; a bottom filling layer filling up a gap between the semiconductor chip and the rewiring layer; a polymer layer surrounding the metal bumps and the semiconductor chip; and an antenna assembly, which is electrically connected to one metal bump through the conductive column and the rewiring layer. By using the foregoing solution, the rewiring layer and the metal bumps facilitate proper packaging design.

公开(公告)号：US10886243B2

公开(公告)日：2021-01-05

申请号：US16674902

申请日：2019-11-05

Applicant: SJ Semiconductor(Jiangyin) Corporation

Inventor： Yenheng Chen ,  Chengchung Lin ,  Chengtar Wu ,  Jangshen Lin

IPC: H01L23/66 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56 ,  H01L23/538 ,  H01L23/367 ,  H01L23/31 ,  H01Q1/22 ,  H01Q1/02 ,  H01L21/683 ,  H01L23/13

Abstract: A method for preparing fan-out antenna packaging structure, includes: providing a carrier and a release layer structure; forming a single-layer antenna structure and a redistribution layer on an upper surface of the release layer; disposing a semiconductor chip electrically connected with the redistribution layer; forming a leading-out conducting wire on the redistribution layer at least on one side of the semiconductor chip; forming a plastic packaging layer wrapping the chip and the leading-out conducting wire; removing part of the plastic packaging layer to expose the chip and the leading-out conducting wire; forming an under-bump metal layer and a solder ball bump on an upper surface of the plastic packaging layer; removing the carrier and the release layer to expose the single-layer antenna structure; soldering a substrate on the solder ball bump; and forming a layer of cooling fins on a second surface of the semiconductor chip.

公开(公告)号：US10854951B2

公开(公告)日：2020-12-01

申请号：US16353990

申请日：2019-03-14

Applicant: SJ Semiconductor(Jiangyin) Corporation

Inventor： Yenheng Chen ,  Chengchung Lin ,  Chengtar Wu ,  Jangshen Lin

IPC: H01L23/48 ,  H01Q1/22 ,  H01Q21/00 ,  H01Q9/04 ,  H01Q21/06 ,  H01L23/522 ,  H01L23/00 ,  H01L23/66

Abstract: The present disclosure provides an antenna package structure and an antenna packaging method for a semiconductor chip. The package structure includes an antenna circuit chip, a first rewiring layer, an antenna structure, a second metal connecting column, a second packaging layer, a second antenna metal layer, and a second metal bump. The antenna circuit chip, the antenna structure, and the second antenna metal layer are interconnected by using two rewiring layers and two layers of metal connecting columns.

公开(公告)号：US11894243B2

公开(公告)日：2024-02-06

申请号：US17531609

申请日：2021-11-19

Applicant: SJ SEMICONDUCTOR (JIANGYIN) CORPORATION

Inventor： Yenheng Chen ,  Chengchung Lin

IPC: H01L21/56 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L21/568 ,  H01L23/49816 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/73267

Abstract: A wafer system-level fan-out packaging structure and a manufacturing method. The method includes: forming a redistribution layer, where the redistribution layer includes a first surface and an opposite second surface; providing a patch element, and bonding the patch element to the second surface; providing a die having a bump disposed on a front side, and bonding the front side of the die to the second surface of the redistribution layer through the bump; and forming a plastic packaging layer on the second surface of the redistribution layer, where the plastic packaging layer covers the patch element, back side and side surfaces of the die. In the wafer system-level fan-out packaging structure and the manufacturing method of the present disclosure, the die and the patch element are packaged in a plastic packaging layer, and the die and the patch element are connected and let out by the redistribution layer.

公开(公告)号：US20230386950A1

公开(公告)日：2023-11-30

申请号：US18142416

申请日：2023-05-02

Applicant: SJ Semiconductor(Jiangyin) Corporation

Inventor： Yenheng Chen ,  Chengchung Lin

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29

CPC classification number: H01L23/3128 ,  H01L21/56 ,  H01L24/11 ,  H01L24/17 ,  H01L24/03 ,  H01L24/09 ,  H01L23/293 ,  H01L2224/14104 ,  H01L2224/02381 ,  H01L2224/02379 ,  H01L2224/11011 ,  H01L2224/14131 ,  H01L2224/02333 ,  H01L2224/03 ,  H01L2224/06505

Abstract: A 3D fan-out packaging structure of an interconnection system with ultra-high density and a method for manufacturing the same are disclosed; the packaging structure includes a first insulating layer, first metal solder pads, a metal pillar, a first chip, a second insulating layer, second metal solder pads, a first encapsulating layer, a first rewiring layer, a second chip, a second encapsulating layer, a second rewiring layer, and a solder ball. The packaging structure adopts the “RDL first” process, and non-soldering interfaces between the first and second metal solder pads help achieve bonding with a spacing of 5-10 μm or even less, much smaller than conventional soldering spacings, thus increasing the number of available I/O ports and obtaining a high-density, highly integrated packaging structure. In addition, in the present disclosure, various chips and electronic components can be integrated together, thereby achieving high-performance system-level packaging with higher flexibility and compatibility.

公开(公告)号：US20230352461A1

公开(公告)日：2023-11-02

申请号：US18139744

申请日：2023-04-26

Applicant: SJ Semiconductor (Jiangyin) Corporation

Inventor： Yenheng Chen ,  Chengchung Lin

IPC: H01L25/10 ,  H01L23/31 ,  H10B80/00 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L25/105 ,  H01L21/4853 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H10B80/00 ,  H01L2224/1601 ,  H01L2224/16057 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1431 ,  H01L2924/1434

Abstract: A three-dimensional fan-out memory package structure and a packaging method are disclosed. The package structure includes a three-dimensional fan-out memory package unit, which includes: a memory chip stack having at least two memory chips laminated in a stepped configuration, each memory chip is provided with a bonding pad; first metal connection pillars formed on the bonding pads; second metal connection pillars; a first encapsulating layer; a first rewiring layer formed on a back side of the memory chip stack; a second rewiring layer formed over a front side of the memory chip stack; and metal bumps. The package structure further includes: at least one peripheral circuit chip electrically connected with the first rewiring layer; and a second encapsulating layer, which encapsulates the peripheral circuit chip. The package structure allows for high-density and high-integration of line width/line spacing. The process time can be shortened, and the efficiency is high.

公开(公告)号：US20220415816A1

公开(公告)日：2022-12-29

申请号：US17851752

申请日：2022-06-28

Applicant: SJ Semiconductor (Jiangyin) Corporation

Inventor： Yenheng Chen ,  Chengchung Lin ,  Jangshen Lin ,  Mingchih Chen

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065

Abstract: The present disclosure provides a wafer-level ASIC 3D integrated substrate, a packaging device and a preparation method. The substrate includes a first wiring layer, conductive pillars, a molding layer, a second wiring layer and solder balls. The first wiring layer includes a first dielectric layer and a first metal wire layer, the first metal wire layer is exposed from a top surface of the first dielectric layer. The second wiring layer includes a second dielectric layer and a second metal wire layer. The conductive pillars are disposed between the first wiring layer and the second wiring layer, two ends of each conductive pillar are electrically connected to the first metal wire layer and the second metal wire layer, respectively. The molding layer molds the conductive pillars. The solder balls are disposed on a side of the second wiring layer and electrically connected to the second metal wire layer.

公开(公告)号：US20220271018A1

公开(公告)日：2022-08-25

申请号：US17564121

申请日：2021-12-28

Applicant: SJ SEMICONDUCTOR (JIANGYIN) CORPORATION

Inventor： Yenheng Chen ,  Chengchung Lin

IPC: H01L25/10 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L25/00

Abstract: The present disclosure provides a double-layer stacked 3D fan-out packaging structure and a method making the structure. The structure includes: a first semiconductor chip, a packaging material layer, a metal connecting pillar, a first rewiring layer, a second rewiring layer, a second semiconductor chip, solder ball bumps, and an underfill layer under the second semiconductor chip. The formed double-layer stacked 3D fan-out packaging structure is capable to package two sets of fan-out wafers in the three-dimension. A single package stacked up after die-cutting has two sets of chips in the third direction. The electrical signals of all chips in a single package can be controlled by arranging a first rewiring layer, a metal connecting post, and the second rewiring layer, so that more chips can be packaged in a single package, thus improving the package integration level and reducing the package volume.

公开(公告)号：US20220271009A1

公开(公告)日：2022-08-25

申请号：US17564124

申请日：2021-12-28

Applicant: SJ SEMICONDUCTOR (JIANGYIN) CORPORATION

Inventor： Yenheng Chen ,  Chengchung Lin

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L23/29 ,  H01L25/00 ,  H01L23/00 ,  H01L21/48

Abstract: The present disclosure provides a double-layer packaged 3D fan-out packaging structure and a method making the same. The structure includes: a first semiconductor chip, a first packaging material layer, a metal connecting pillar, a first rewiring layer, a second rewiring layer, a second semiconductor chip, solder ball bumps, and a second packaging material layer. The formed double-layer packaged 3D fan-out packaging structure can package two sets of fan-out wafers in the three-dimensional direction. A single package stacked up after die-cutting has two sets of chips in the third direction. The electrical signals of all chips in a single package can be controlled by arranging a first rewiring layer, a metal connecting post, and the second rewiring layer, so that more chips can be packaged in a single package, thus improving the integration level of the package and reducing the package volume.