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公开(公告)号：US20230386967A1
公开(公告)日：2023-11-30
申请号：US18142424
申请日：2023-05-02
发明人： Chengchung Lin , Jin Yang
IPC分类号： H01L23/473 , H01L25/065 , H01L25/18 , H10B80/00
CPC分类号： H01L23/473 , H01L25/0655 , H01L25/18 , H10B80/00
摘要： A wafer packaging system and a method for manufacturing the same are disclosed; the system comprises: a silicon substrate having a first surface and a second surface opposite to the first surface; a rewiring layer disposed on the first surface of the silicon substrate; a plurality of chips bonded over the rewiring layer; and a structural reinforcement layer, fixed to the second surface of the silicon substrate, wherein liquid cooling channels are formed inside the structural reinforcement layer. The wafer packaging system of the present disclosure integrates a plurality of chips with different functions onto one full-wafer-size platform to improve the packaging performance. A structural reinforcement layer is added to the packaging system, which supports a large silicon substrate platform and enhances the structural rigidity of the whole packaging system. The structural reinforcement layer, along with liquid cooling channels, provides a heat conducting path for heat generated by the system.
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公开(公告)号：US11502392B2
公开(公告)日：2022-11-15
申请号：US17108953
申请日：2020-12-01
发明人： Yenheng Chen , Chengchung Lin , Chengtar Wu , Jangshen Lin
IPC分类号： H01L23/34 , H01Q1/22 , H01L23/66 , H01L23/00 , H01L23/498 , H01L21/48 , H01L21/683
摘要： The present disclosure provides a packaging structure and a packaging method for an antenna. The packaging structure comprises a redistribution layer, having a first surface and an opposite second surface; a first metal joint pin, formed on the second surface of the redistribution layer; a first packaging layer, disposed on the redistribution layer covering the first metal joint pin; a first antenna metal layer, patterned on the first packaging layer, and a portion of the first antenna metal layer electrically connects with the first metal joint pin; a second metal joint pin, formed on the first antenna metal layer; a second packaging layer, disposed on the first antenna metal layer covering the second metal joint pin; a second antenna metal layer, formed on the second packaging layer; and a metal bump and an antenna circuit chip, bonded to the first surface of the redistribution layer.
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3.发明申请公开(公告)号：US20220165654A1
公开(公告)日：2022-05-26
申请号：US17531631
申请日：2021-11-19
发明人： Yenheng CHEN , Chengchung Lin
IPC分类号： H01L23/498 , H01L23/00 , H01L21/48 , H01L23/48 , H01L23/29
摘要： A wafer system-level three-dimensional fan-out packaging structure and a manufacturing method therefor. The method includes: forming a redistribution layer, where the redistribution layer includes a first surface and a second surface opposite to each other; forming a conductive connecting post on the second surface of the redistribution layer; bonding the patch element to the second surface of the redistribution layer; forming a plastic packaging layer on the second surface of the redistribution layer; thinning the plastic packaging layer; forming a plurality of solder bumps on a side of the plastic packaging layer that faces away from the redistribution layer; cutting the redistribution layer and the plastic packaging layer to obtain a number of first package structures; and bonding a second package layer to the first surface of the redistribution layer of one of the first package structures.
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公开(公告)号：US20220084925A1
公开(公告)日：2022-03-17
申请号：US17476340
申请日：2021-09-15
发明人： Yenheng CHEN , Chengchung Lin
IPC分类号： H01L23/498 , H01L21/48 , H01L23/00 , H01L25/10
摘要： The present disclosure provides a fan-out packaging structure and a method for fabricating the fan-out packaging. The fan-out packaging structure includes a first redistribution layer, a second redistribution layer, metal connecting posts, a semiconductor chip, a first filling layer, a first packaging layer, a stacked chip package, a passive element, a second filling layer, a second packaging layer, and metal bumps. By means of the present disclosure, various chips having different functions can be integrated into one packaging structure, thereby improving the integration of the fan-out packaging structure. By means of the first redistribution layer, the second redistribution layer, and the metal connecting posts, a three-dimensional vertical stacked packaging is achieved. In this way, the integration level of the packaging structure can be effectively improved, and the conduction path can be significantly shortened, thereby reducing the power consumption, increasing the signal transmission speed, and increasing the data processing capacity.
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公开(公告)号：US11121065B2
公开(公告)日：2021-09-14
申请号：US16232988
申请日：2018-12-26
发明人： Yenheng Chen , Chentar Wu , Chengchung Lin
IPC分类号： H01L23/498 , H01L23/15 , H01L23/31 , H01L23/66
摘要： The present application provides a semiconductor packaging structure with an antenna assembly, including: a substrate with through-substrate-via holes; a rewiring layer, located on the substrate; metal bumps, located on and electrically connected to the rewiring layer; a semiconductor chip, located on a surface of the rewiring layer and electrically connected to the rewiring layer; a conductive column, filling in the via hole; a bottom filling layer filling up a gap between the semiconductor chip and the rewiring layer; a polymer layer surrounding the metal bumps and the semiconductor chip; and an antenna assembly, which is electrically connected to one metal bump through the conductive column and the rewiring layer. By using the foregoing solution, the rewiring layer and the metal bumps facilitate proper packaging design.
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公开(公告)号：US10886243B2
公开(公告)日：2021-01-05
申请号：US16674902
申请日：2019-11-05
发明人： Yenheng Chen , Chengchung Lin , Chengtar Wu , Jangshen Lin
IPC分类号： H01L23/66 , H01L21/48 , H01L23/00 , H01L21/56 , H01L23/538 , H01L23/367 , H01L23/31 , H01Q1/22 , H01Q1/02 , H01L21/683 , H01L23/13
摘要： A method for preparing fan-out antenna packaging structure, includes: providing a carrier and a release layer structure; forming a single-layer antenna structure and a redistribution layer on an upper surface of the release layer; disposing a semiconductor chip electrically connected with the redistribution layer; forming a leading-out conducting wire on the redistribution layer at least on one side of the semiconductor chip; forming a plastic packaging layer wrapping the chip and the leading-out conducting wire; removing part of the plastic packaging layer to expose the chip and the leading-out conducting wire; forming an under-bump metal layer and a solder ball bump on an upper surface of the plastic packaging layer; removing the carrier and the release layer to expose the single-layer antenna structure; soldering a substrate on the solder ball bump; and forming a layer of cooling fins on a second surface of the semiconductor chip.
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公开(公告)号：US10854951B2
公开(公告)日：2020-12-01
申请号：US16353990
申请日：2019-03-14
发明人： Yenheng Chen , Chengchung Lin , Chengtar Wu , Jangshen Lin
IPC分类号： H01L23/48 , H01Q1/22 , H01Q21/00 , H01Q9/04 , H01Q21/06 , H01L23/522 , H01L23/00 , H01L23/66
摘要： The present disclosure provides an antenna package structure and an antenna packaging method for a semiconductor chip. The package structure includes an antenna circuit chip, a first rewiring layer, an antenna structure, a second metal connecting column, a second packaging layer, a second antenna metal layer, and a second metal bump. The antenna circuit chip, the antenna structure, and the second antenna metal layer are interconnected by using two rewiring layers and two layers of metal connecting columns.
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公开(公告)号：US10593641B2
公开(公告)日：2020-03-17
申请号：US15560965
申请日：2016-05-20
发明人： Yuedong Qiu , Chengchung Lin
IPC分类号： H01L23/48 , H01L23/00 , H01L25/065 , H01L21/683 , H01L23/538 , H01L23/528 , H01L21/56 , H01L23/485 , H01L23/31
摘要： A packaging method and a package structure of a fan-out chip are disclosed. The package structure comprises a first chip with bumps and a second chip without bumps, a first dielectric layer formed on a surface of the second chip and through-holes fabricated in the first dielectric layer; a plastic package material; a second dielectric layer; a metal redistribution layer for interconnecting within and between the first chip and the second chip; under bump metallization layers and micro-bumps. By fabricating the dielectric layers with the through-holes on the surfaces of the first chip and the second chip, exposing the bumps of the first chip and metal pads of the second chip and subsequently fabricating the metal redistribution layer, the interconnections within and between the first chip and the second chip are achieved and thereby the integrated package of the first chip and the second chip is achieved.
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公开(公告)号：US11894243B2
公开(公告)日：2024-02-06
申请号：US17531609
申请日：2021-11-19
发明人： Yenheng Chen , Chengchung Lin
IPC分类号： H01L21/56 , H01L23/498 , H01L23/00
CPC分类号： H01L21/568 , H01L23/49816 , H01L24/19 , H01L2224/04105 , H01L2224/12105 , H01L2224/73267
摘要： A wafer system-level fan-out packaging structure and a manufacturing method. The method includes: forming a redistribution layer, where the redistribution layer includes a first surface and an opposite second surface; providing a patch element, and bonding the patch element to the second surface; providing a die having a bump disposed on a front side, and bonding the front side of the die to the second surface of the redistribution layer through the bump; and forming a plastic packaging layer on the second surface of the redistribution layer, where the plastic packaging layer covers the patch element, back side and side surfaces of the die. In the wafer system-level fan-out packaging structure and the manufacturing method of the present disclosure, the die and the patch element are packaged in a plastic packaging layer, and the die and the patch element are connected and let out by the redistribution layer.
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10.发明公开公开(公告)号：US20230386950A1
公开(公告)日：2023-11-30
申请号：US18142416
申请日：2023-05-02
发明人： Yenheng Chen , Chengchung Lin
CPC分类号： H01L23/3128 , H01L21/56 , H01L24/11 , H01L24/17 , H01L24/03 , H01L24/09 , H01L23/293 , H01L2224/14104 , H01L2224/02381 , H01L2224/02379 , H01L2224/11011 , H01L2224/14131 , H01L2224/02333 , H01L2224/03 , H01L2224/06505
摘要： A 3D fan-out packaging structure of an interconnection system with ultra-high density and a method for manufacturing the same are disclosed; the packaging structure includes a first insulating layer, first metal solder pads, a metal pillar, a first chip, a second insulating layer, second metal solder pads, a first encapsulating layer, a first rewiring layer, a second chip, a second encapsulating layer, a second rewiring layer, and a solder ball. The packaging structure adopts the “RDL first” process, and non-soldering interfaces between the first and second metal solder pads help achieve bonding with a spacing of 5-10 μm or even less, much smaller than conventional soldering spacings, thus increasing the number of available I/O ports and obtaining a high-density, highly integrated packaging structure. In addition, in the present disclosure, various chips and electronic components can be integrated together, thereby achieving high-performance system-level packaging with higher flexibility and compatibility.
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