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18 条记录 (耗时 0.018 秒)

    Method, apparatus and system to interconnect packaged integrated circuit dies
    3.
    发明授权
    Method, apparatus and system to interconnect packaged integrated circuit dies 有权

    公开(公告)号：US10396055B2

    公开(公告)日：2019-08-27

    申请号：US15749760

    申请日：2015-09-25

    申请人： Intel Corporation

    发明人： Yong She ,  John G. Meyers ,  Zhicheng Ding ,  Richard Patten

    IPC分类号： H01L23/48 ,  H01L25/065 ,  H01L23/488 ,  H01L23/00 ,  H01L23/49 ,  H01L23/50 ,  H01L25/00 ,  H01L23/538

    摘要： Techniques and mechanisms for interconnecting stacked integrated circuit (IC) dies. In an embodiment, a first end of a wire is coupled to a first IC die of a stack, where a second end of the wire is further anchored to the stack independent of the coupled first end. A package material is subsequently disposed around IC dies of the stack and a first portion of the wire that includes the first end. Two-point anchoring of the wire to the stack aids in providing mechanical support to resist movement that might otherwise displace and/or deform the wire while the package material is deposited. In another embodiment, the first portion of the wire is separated from the rest of the wire, and a redistribution layer is coupled to the first portion to enable interconnection between the first IC die and another IC die of the stack.

    DIE STACK WITH CASCADE AND VERTICAL CONNECTIONS
    4.
    发明申请
    DIE STACK WITH CASCADE AND VERTICAL CONNECTIONS 审中-公开

    公开(公告)号：US20180366441A1

    公开(公告)日：2018-12-20

    申请号：US15780506

    申请日：2015-12-02

    申请人： Intel Corporation

    发明人： Min-Tih Ted Lai ,  Florence R. Pon ,  Yuhong Cai ,  John G. Meyers

    IPC分类号： H01L25/065 ,  H01L25/00

    摘要： An electronic assembly includes a plurality of electronic die arranged into shingles, each shingle having a multiple offset stacked die coupled by cascading connections. Each shingle is arranged in a stack of shingles with alternate shingles having die stacked in opposite directions and offset in a zigzag manner to facilitate vertical electrical connections from a top of the electronic assembly to a bottom die of each shingle.

    Method, apparatus and system to interconnect packaged integrated circuit dies
    5.
    发明授权
    Method, apparatus and system to interconnect packaged integrated circuit dies 有权

    公开(公告)号：US10910347B2

    公开(公告)日：2021-02-02

    申请号：US16516695

    申请日：2019-07-19

    申请人： Intel Corporation

    发明人： Yong She ,  John G. Meyers ,  Zhicheng Ding ,  Richard Patten

    IPC分类号： H01L25/065 ,  H01L23/488 ,  H01L23/00 ,  H01L23/49 ,  H01L23/50 ,  H01L25/00 ,  H01L23/538

    摘要： Techniques and mechanisms for interconnecting stacked integrated circuit (IC) dies. In an embodiment, a first end of a wire is coupled to a first IC die of a stack, where a second end of the wire is further anchored to the stack independent of the coupled first end. A package material is subsequently disposed around IC dies of the stack and a first portion of the wire that includes the first end. Two-point anchoring of the wire to the stack aids in providing mechanical support to resist movement that might otherwise displace and/or deform the wire while the package material is deposited. In another embodiment, the first portion of the wire is separated from the rest of the wire, and a redistribution layer is coupled to the first portion to enable interconnection between the first IC die and another IC die of the stack.

    METHOD, APPARATUS AND SYSTEM TO INTERCONNECT PACKAGED INTEGRATED CIRCUIT DIES
    6.
    发明申请
    METHOD, APPARATUS AND SYSTEM TO INTERCONNECT PACKAGED INTEGRATED CIRCUIT DIES 审中-公开

    公开(公告)号：US20190341372A1

    公开(公告)日：2019-11-07

    申请号：US16516695

    申请日：2019-07-19

    申请人： Intel Corporation

    发明人： Yong She ,  John G. Meyers ,  Zhicheng Ding ,  Richard Patten

    IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/50 ,  H01L23/488 ,  H01L23/49 ,  H01L25/00

    摘要： Techniques and mechanisms for interconnecting stacked integrated circuit (IC) dies. In an embodiment, a first end of a wire is coupled to a first IC die of a stack, where a second end of the wire is further anchored to the stack independent of the coupled first end. A package material is subsequently disposed around IC dies of the stack and a first portion of the wire that includes the first end. Two-point anchoring of the wire to the stack aids in providing mechanical support to resist movement that might otherwise displace and/or deform the wire while the package material is deposited. In another embodiment, the first portion of the wire is separated from the rest of the wire, and a redistribution layer is coupled to the first portion to enable interconnection between the first IC die and another IC die of the stack.

    MULTI-POINT STACKED DIE WIREBONDING FOR IMPROVED POWER DELIVERY
    7.
    发明申请
    MULTI-POINT STACKED DIE WIREBONDING FOR IMPROVED POWER DELIVERY 审中-公开

    公开(公告)号：US20190326249A1

    公开(公告)日：2019-10-24

    申请号：US16465046

    申请日：2016-12-29

    申请人： Intel Corporation

    发明人： John G. Meyers ,  Florence R. Pon

    IPC分类号： H01L23/00 ,  G11C5/06 ,  H01L25/065 ,  H01L21/56 ,  H01L23/31

    摘要： An apparatus is provided which comprises: a plurality of circuit regions in an integrated circuit die, wherein the circuit regions comprise circuit components formed in semiconductor material, a plurality of interconnect regions to route power to the circuit regions from a surface of the integrated circuit die, wherein the interconnect regions comprise conductive traces within dielectric material and a plurality of wirebond pads on the surface of the integrated circuit die, wherein the wirebond pads comprise a substantially even distribution over the surface of the integrated circuit die. Other embodiments are also disclosed and claimed.