Abstract:
A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.
Abstract:
A display device includes a thin film transistor on a base substrate and a signal wiring electrically connected to the thin film transistor. The signal wiring includes a main conductive layer including copper, and a capping layer including titanium the capping layer overlapping a portion of an upper surface of the main conductive layer. The signal wiring has a taper angle in a range of about 70° to about 90°. A thickness of the capping layer is in a range of about 100 Å to about 300 Å, and a thickness of the main conductive layer is in a range of about 1,000 Å to about 20,000 Å.
Abstract:
An manufacturing method of a display device may include the following steps: forming a transistor on a substrate; forming an insulating layer on the transistor; forming a conductive layer including silver on the insulating layer; forming a photosensitive member on the conductive layer; forming an electrode of a light-emitting element by etching the conductive layer; performing plasma treatment on a structure that comprises the electrode, the plasma treatment using a gas including a halogen; and removing a product that is resulted from the plasma treatment.
Abstract:
According to an exemplary embodiment, a display substrate includes a gate metal pattern comprising a gate electrode, an active pattern disposed on the gate pattern and a source metal pattern disposed on the active pattern. The source metal pattern includes a first lower pattern disposed on the active pattern, a second lower pattern disposed on the first lower pattern, a low-resistance metal pattern disposed on the second lower pattern, and an upper pattern disposed on the low-resistance metal pattern. The first lower pattern, the second lower pattern, and the upper pattern each include a material that is the same.
Abstract:
An OLED device includes a substrate, a first active layer, a first gate electrode, a second gate electrode, first source and first drain electrodes, a first high dielectric constant (high-k) insulation structure, and a light emitting structure. The substrate has a first region and a second region. The first active layer is disposed in the first region on the substrate. The first gate electrode is disposed on the first active layer, and has a first thickness. The second gate electrode is disposed on the first gate electrode. The first source electrode and first drain electrode are disposed on the second gate electrode, and constitutes a first semiconductor element together with the first active layer and the first gate electrode. The first high-k insulation structure is disposed between the first gate electrode and the second gate electrode, and is spaced apart from the first source electrode and first drain electrode.
Abstract:
A thin film transistor array panel includes: a substrate, a gate line positioned on the substrate and including a gate electrode, a semiconductor layer positioned on the substrate and including an oxide semiconductor, a data wire layer positioned on the substrate and including a data line crossing the gate line, a source electrode connected to the data line, and a drain electrode facing the source electrode, and a capping layer covering the data wire layer, in which an end of the capping layer is inwardly recessed as compared to an end of the data wire layer.
Abstract:
A light emitting display device and a car including the same according to embodiments include: a substrate; a plurality of light emitting diodes that are disposed above the substrate and include a plurality of light emitting layers; a pixel defining layer that has openings corresponding to the plurality of light emitting layers; and a plurality of light blocking patterns that are disposed on the pixel defining layer and the plurality of light emitting layers, and extend in a first direction. Each of the plurality of light blocking patterns includes a first portion and a second portion formed on the first portion and having a width decreasing toward an upper portion thereof.
Abstract:
A display device includes, a light emitting diode disposed on a substrate, and including an emission layer, an encapsulation layer disposed on the light emitting diode, a first layer disposed on the encapsulation layer and including an opening, a light blocking pattern disposed in the opening and extending in a first direction, and a second layer disposed on the first layer and the light blocking pattern. A refractive index of the first layer and a refractive index of the second layer are different from each other.
Abstract:
A display device comprises a transistor layer that includes a display area and a pad area disposed adjacent to the display area, an emission layer disposed in the display area on the transistor layer, a first display insulating layer disposed on the emission layer, and an insulating layer disposed in the pad area on the transistor layer, the insulating layer and the first display insulating layer including a same material, and the insulating layer having a step.
Abstract:
A display substrate includes a substrate, a first gate electrode on the substrate, a first gate insulating layer on the first gate electrode, an active layer on the first gate insulating layer, a second gate insulating layer on the active layer, a second gate electrode on the second gate insulating layer, an interlayer insulating layer on the second gate electrode, a first electrode on the interlayer insulating layer to contact a top surface, a side wall, and a bottom surface of the active layer via a first contact hole through the interlayer insulating layer, the second gate insulating layer, the active layer, and a portion of the first gate insulating layer, and a second electrode on the interlayer insulating layer to contact the first gate electrode via a second contact hole through the interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer.