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公开(公告)号：US20200058727A1
公开(公告)日：2020-02-20
申请号：US16521394
申请日：2019-07-24
Inventor： Sang Gab KIM , Hyun Min CHO , Tae Sung KIM , Yu-Gwang JEONG , Su Bin BAE , Jin Seock KIM , Sang Gyun KIM , Hyo Min KO , Kil Won CHO , Han Sol LEE
IPC: H01L27/32
Abstract: An manufacturing method of a display device may include the following steps: forming a transistor on a substrate; forming an insulating layer on the transistor; forming a conductive layer including silver on the insulating layer; forming a photosensitive member on the conductive layer; forming an electrode of a light-emitting element by etching the conductive layer; performing plasma treatment on a structure that comprises the electrode, the plasma treatment using a gas including a halogen; and removing a product that is resulted from the plasma treatment.
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公开(公告)号：US20210384287A1
公开(公告)日：2021-12-09
申请号：US17445471
申请日：2021-08-19
Inventor： Sang Gab KIM , Hyun Min CHO , Tae Sung KIM , Yu-Gwang JEONG , Su Bin BAE , Jin Seock KIM , Sang Gyun KIM , Hyo Min KO , Kil Won CHO , Hansol LEE
IPC: H01L27/32
Abstract: An manufacturing method of a display device may include the following steps: forming a transistor on a substrate; forming an insulating layer on the transistor; forming a conductive layer including silver on the insulating layer; forming a photosensitive member on the conductive layer; forming an electrode of a light-emitting element by etching the conductive layer; performing plasma treatment on a structure that comprises the electrode, the plasma treatment using a gas including a halogen; and removing a product that is resulted from the plasma treatment.
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公开(公告)号：US20240121989A1
公开(公告)日：2024-04-11
申请号：US18229766
申请日：2023-08-03
Applicant: Samsung Display Co., LTD.
Inventor： Da Woon JUNG , Su Bin BAE , Tae Wook KANG , Sang Gab KIM , Yun Jong YEO , Yu Gwang JEONG
IPC: H10K59/122 , H10K59/12 , H10K59/38 , H10K59/40
CPC classification number: H10K59/122 , H10K59/1201 , H10K59/38 , H10K59/40
Abstract: A display device includes: a first pixel electrode disposed in a first emission area, on a substrate; an insulating layer covering edges of the first pixel electrode; a first light-emitting layer disposed on the first pixel electrode and the insulating layer; a first common electrode disposed on the first light-emitting layer; banks disposed on the insulating layer and surrounding the first emission area; and a first organic pattern surrounding the first emission area, disposed on the banks, and including the same material as the first light-emitting layer. Side surfaces of each of the banks are spaced apart from side surfaces of the insulating layer.
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公开(公告)号：US20230240104A1
公开(公告)日：2023-07-27
申请号：US18094393
申请日：2023-01-09
Applicant: Samsung Display Co., Ltd.
Inventor： DAWOON JUNG , Yu-Gwang JEONG , Su Bin BAE , Sung Won CHO
IPC: H10K59/131 , G09G3/3233 , H10K59/12
CPC classification number: H10K59/131 , G09G3/3233 , H10K59/1201 , G09G2300/0842 , G09G2300/0819 , G09G2300/0861 , G09G2300/0426
Abstract: A display device includes the following elements: a semiconductor layer positioned on a substrate; a first gate insulating layer positioned on the semiconductor layer; a first gate conductive layer positioned on the first gate insulating layer; a second gate insulating layer positioned on the first gate conductive layer; a second gate conductive layer positioned on the second gate insulating layer; a first insulating layer positioned on the second gate conductive layer; a first contact hole passing through the first insulating layer, the second gate insulating layer, and the first gate insulating layer; a second contact hole passing through the first insulating layer; and a third contact hole passing through the first insulating layer and the second gate insulating layer. A cross-section of the first insulating layer in a plane perpendicular to the substrate has a curved profile.
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公开(公告)号：US20180175178A1
公开(公告)日：2018-06-21
申请号：US15895464
申请日：2018-02-13
Applicant: Samsung Display Co., Ltd.
Inventor： Jung Yun JO , Su Bin BAE , Ki Seong SEO
IPC: H01L29/66 , H01L29/786 , H01L29/45 , H01L29/417 , H01L21/4763 , H01L21/02
CPC classification number: H01L29/66969 , H01L21/02554 , H01L21/02565 , H01L21/47635 , H01L29/41733 , H01L29/45 , H01L29/78606 , H01L29/7869
Abstract: There is provided a method of manufacturing an oxide thin film transistor (TFT). The method includes forming a gate electrode on a substrate, forming a gate insulating layer on the gate electrode, forming an oxide semiconductor layer including a channel layer on the gate insulating layer, forming a source electrode and a drain electrode separated from each other on the oxide semiconductor layer, first plasma processing the substrate on which the source electrode and the drain electrode are formed at a carbon (C) atmosphere, secondly plasma processing the substrate at a nitrogen oxide atmosphere, and sequentially forming a first protective layer and a second protective layer on the substrate.
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Patent Agency Ranking
公开(公告)号：US20230200113A1
公开(公告)日：2023-06-22
申请号：US17881693
申请日：2022-08-05
Applicant: Samsung Display Co., LTD.
Inventor： Yu-Gwang JEONG , Jin-Su BYUN , Sung Won CHO , Su Bin BAE , DAWOON JUNG
CPC classification number: H01L51/5253 , H01L27/323 , H01L51/56 , H01L27/3276 , H01L2227/323
Abstract: A display device includes a display area, anon-display area, and a pad part in the non-display area and exposed to outside the display device. The pad part includes a conductive part, and an insulating part defining an opening exposing the conductive part to outside the pad part. The insulating part includes in order from the conductive part a first insulating layer defining a first opening, and a second insulating layer facing the first insulating layer and defining a second opening which is wider than the first opening.
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公开(公告)号：US20230180537A1
公开(公告)日：2023-06-08
申请号：US17860206
申请日：2022-07-08
Applicant: Samsung Display Co., Ltd.
Inventor： DAWOON JUNG , Dae Won CHOI , Su Bin BAE , Yu-Gwang JEONG
CPC classification number: H01L27/3248 , H01L51/5072 , H01L51/5056 , H01L27/3246 , H01L2251/305
Abstract: A light emitting display device includes a substrate, a transistor, a first insulating layer, a second insulating layer, a pixel electrode, a conductive member, a third insulating layer, and a light emitting material layer. The transistor overlaps the substrate. The first insulating layer overlaps the transistor. The second insulating layer overlaps the first insulating layer. The pixel electrode directly contacts the second insulating layer and is electrically connected to the transistor. The conductive member directly contacts at least one of the first insulating layer and the second insulating layer. The third insulating layer overlaps the second insulating layer, includes a hole, and includes an opening. The hole exposes the pixel electrode. The opening exposes the conductive member. The light emitting material layer overlaps the pixel electrode inside the hole, overlaps the third insulating layer, and has a discontinuity inside the opening.
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公开(公告)号：US20190123065A1
公开(公告)日：2019-04-25
申请号：US16215520
申请日：2018-12-10
Applicant: Samsung Display Co., Ltd.
Inventor： Yu-Gwang JEONG , Hyun Min CHO , Su Bin BAE , Shin II CHOI , Sang Gab KIM
IPC: H01L27/12 , H01L21/311 , H01L29/417
CPC classification number: H01L27/124 , G02F1/1368 , G02F2201/123 , H01L21/31116 , H01L21/31144 , H01L27/1218 , H01L27/1288 , H01L27/3246 , H01L27/3248 , H01L27/3262 , H01L27/3276 , H01L29/41733 , H01L29/78633
Abstract: A transistor array panel is manufactured by a method that reduces or obviates the need for highly selective etching agents or complex processes requiring multiple photomasks to create contact holes. The panel includes: a substrate; a buffer layer positioned on the substrate; a semiconductor layer positioned on the buffer layer; an intermediate insulating layer positioned on the semiconductor layer; and an upper conductive layer positioned on the intermediate insulating layer, wherein the semiconductor layer includes a first contact hole, the intermediate insulating layer includes a second contact hole positioned in an overlapping relationship with the first contact hole, and the upper conductive layer is in contact with a side surface of the semiconductor layer in the first contact hole.
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公开(公告)号：US20170278867A1
公开(公告)日：2017-09-28
申请号：US15465154
申请日：2017-03-21
Applicant: Samsung Display Co. Ltd.
Inventor： Yu Gwang JEONG , Su Bin BAE , Hyun Min CHO , Sang Gab KIM
IPC: H01L27/12
Abstract: A display device may include a substrate, an active pattern layer, a gate insulating layer, a first metal pattern layer, an interlayer insulating layer, a second metal pattern layer, and a passivation film. The active pattern layer may be disposed on the substrate. The gate insulating layer may be disposed on the active pattern layer. The first metal pattern layer may be disposed on the gate insulating layer. The interlayer insulating layer may be disposed on the first metal pattern layer. The second metal pattern layer may be disposed on the interlayer insulating layer. The passivation film may be disposed on the side wall of the second metal pattern layer.
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10.发明申请ELECTRODE PATTERN, MANUFACTURING METHOD THEREOF, AND TOUCH SENSOR INCLUDING THE SAME 审中-公开电极图案及其制造方法，以及包括其的触摸传感器公开(公告)号：US20160170521A1
公开(公告)日：2016-06-16
申请号：US14712953
申请日：2015-05-15
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Shin Il CHOI , Jae Neung KIM , Su Bin BAE , Yu-Gwang JEONG
CPC classification number: G06F3/044 , G06F2203/04103 , G06F2203/04111 , G06F2203/04112
Abstract: A transparent electrode pattern includes a first electrode including a first lower conductive layer and a first upper conductive layer located on the first lower conductive layer and a second electrode spaced apart from the first electrode and including a second lower conductive layer and a second upper conductive layer positioned on the second lower conductive layer. The first and second lower conductive layers may include a metal nanowire. The first and second upper conductive layers may include a transparent conductive material that is dry-etchable.
Abstract translation: 透明电极图案包括第一电极，其包括第一下导电层和位于第一下导电层上的第一上导电层和与第一电极间隔开的第二电极，并且包括第二下导电层和第二上导电层 位于第二下导电层上。 第一和第二下导电层可以包括金属纳米线。 第一和第二上导电层可以包括可干蚀刻的透明导电材料。
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