公开(公告)号：US20170317104A1

公开(公告)日：2017-11-02

申请号：US15380596

申请日：2016-12-15

Applicant: Samsung Display Co., Ltd.

Inventor： Yu-Gwang JEONG ,  Hyun Min CHO ,  Su Bin BAE ,  Shin II CHOI ,  Sang Gab KIM

IPC: H01L27/12 ,  H01L21/311 ,  H01L27/32 ,  G02F1/1368

CPC classification number: H01L27/124 ,  G02F1/1368 ,  G02F2201/123 ,  H01L21/31116 ,  H01L21/31144 ,  H01L27/1218 ,  H01L27/1288 ,  H01L27/3246 ,  H01L27/3248 ,  H01L27/3262 ,  H01L27/3276 ,  H01L29/41733

Abstract: A transistor array panel is manufactured by a method that reduces or obviates the need for highly selective etching agents or complex processes requiring multiple photomasks to create contact holes. The panel includes: a substrate; a buffer layer positioned on the substrate; a semiconductor layer positioned on the buffer layer; an intermediate insulating layer positioned on the semiconductor layer; and an upper conductive layer positioned on the intermediate insulating layer, wherein the semiconductor layer includes a first contact hole, the intermediate insulating layer includes a second contact hole positioned in an overlapping relationship with the first contact hole, and the upper conductive layer is in contact with a side surface of the semiconductor layer in the first contact hole.

公开(公告)号：US20190123065A1

公开(公告)日：2019-04-25

申请号：US16215520

申请日：2018-12-10

Applicant: Samsung Display Co., Ltd.

Inventor： Yu-Gwang JEONG ,  Hyun Min CHO ,  Su Bin BAE ,  Shin II CHOI ,  Sang Gab KIM

IPC: H01L27/12 ,  H01L21/311 ,  H01L29/417

CPC classification number: H01L27/124 ,  G02F1/1368 ,  G02F2201/123 ,  H01L21/31116 ,  H01L21/31144 ,  H01L27/1218 ,  H01L27/1288 ,  H01L27/3246 ,  H01L27/3248 ,  H01L27/3262 ,  H01L27/3276 ,  H01L29/41733 ,  H01L29/78633

Abstract: A transistor array panel is manufactured by a method that reduces or obviates the need for highly selective etching agents or complex processes requiring multiple photomasks to create contact holes. The panel includes: a substrate; a buffer layer positioned on the substrate; a semiconductor layer positioned on the buffer layer; an intermediate insulating layer positioned on the semiconductor layer; and an upper conductive layer positioned on the intermediate insulating layer, wherein the semiconductor layer includes a first contact hole, the intermediate insulating layer includes a second contact hole positioned in an overlapping relationship with the first contact hole, and the upper conductive layer is in contact with a side surface of the semiconductor layer in the first contact hole.