公开(公告)号：US20240363164A1

公开(公告)日：2024-10-31

申请号：US18765452

申请日：2024-07-08

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Po-Hao TSENG ,  Feng-Min LEE ,  Ming-Hsiu Lee

IPC: G11C15/04 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26

CPC classification number: G11C15/046 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26

Abstract: The application provides a content addressable memory (CAM) cell, a CAM memory device and an operation method thereof, and a method for searching and comparing data. The CAM cell includes a first flash memory cell having a first terminal for receiving a first search voltage; and a second flash memory cell having a first terminal for receiving a second search voltage, a second terminal of the first flash memory cell electrically connected to a second terminal of the second flash memory cell, wherein the first flash memory cell and the second flash memory cell are serially connected; and a storage data of the CAM cell is based on a combination of a plurality of threshold voltages of the first flash memory cell and the second flash memory cell.

公开(公告)号：US20240257873A1

公开(公告)日：2024-08-01

申请号：US18162728

申请日：2023-02-01

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Po-Hao TSENG ,  Yu-Hsuan LIN ,  Tian-Cih BO ,  Feng-Min LEE ,  Yu-Yu LIN

IPC: G11C15/04

CPC classification number: G11C15/046

Abstract: A hybrid in-memory search (IMS) content addressable memory (CAM) cell includes: a first IMS CAM cell; and a second IMS CAM cell, coupled to the first IMS CAM cell. The first IMS CAM cell and the second IMS CAM cell are of different types. When the hybrid IMS CAM cell stores a storage data, the first IMS CAM cell stores a first part of the storage data and the second IMS CAM cell stores the storage data or a second part of the storage data.

公开(公告)号：US20230075257A1

公开(公告)日：2023-03-09

申请号：US18055855

申请日：2022-11-16

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Ming-Hsiu LEE ,  Po-Hao TSENG

IPC: G11C7/10 ,  G11C15/04

Abstract: A multilevel content addressable memory, a multilevel coding method and a multilevel searching method are provided. The multilevel coding method includes the following steps. A highest decimal value of a multilevel-bit binary data is obtained. A length of a digital string data is set as being the highest decimal value of the multilevel-bit binary data. The multilevel-bit binary data is converted into the digital string data. If a content of the multilevel-bit binary data is an exact value, a number of an indicating bit in the digital string data is the exact value.

公开(公告)号：US20210224041A1

公开(公告)日：2021-07-22

申请号：US16807194

申请日：2020-03-03

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Po-Hao TSENG ,  Ming-Hsiu LEE ,  Yu-Hsuan LIN

IPC: G06F7/58 ,  G06F9/30 ,  G06F1/10 ,  G06F1/14

Abstract: A random number generator, a random number generating circuit, and a random number generating method are provided. The random number generating circuit includes the random number generator and executes the random number generating method. The random number generator includes a shift register having N storage elements and a combinational logic circuit. The N storage elements receive a random seed in a static state and repetitively perform a bit shift operation in a plurality of clock cycles. The combinational logic circuit generates an output sequence based on the random seed and a random bitstream received from an external source.

公开(公告)号：US20240370228A1

公开(公告)日：2024-11-07

申请号：US18143777

申请日：2023-05-05

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Po-Hao TSENG

IPC: G06F7/544 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26

Abstract: A system based on computational memory and memory systems, such as embodied in computational solid state drive (SSD) technology, as described herein, reduces processor utilization and/or bus bandwidth utilization. The system is enabled to perform computational techniques (e.g., searching, computing, and/or accessing) using resources of the computational SSDs, rather than processor and/or bus resources, thus reducing or minimizing information movement between processing elements and storage devices. Computational SSD technology enables managing, organizing, selecting, and analyzing ever increasing data volume in real time. A computational SSD is enabled to store and to operate on data locally, e.g., using resources of the computational SSD. Thus, processing, storage, and bandwidth requirements of a system are reduced by using the computational SSD.

公开(公告)号：US20240339162A1

公开(公告)日：2024-10-10

申请号：US18744776

申请日：2024-06-17

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Po-Hao TSENG

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30

CPC classification number: G11C16/3404 ,  G11C16/08 ,  G11C16/102 ,  G11C16/26 ,  G11C16/30

Abstract: An encoding method is provided for a memory device which includes an in-memory search (IMS) array having several memory units. The memory units in a same horizontal row are coupled to a first driving circuit through corresponding word lines and coupled to a sensing circuit through a match signal line. Every 2N adjacent memory units in the same horizontal row are arranged as a memory cell. An original data of M-bits is encoded to an encoded data of 2N-bits with a first encoded area including the first to N-th bits of the encoded data and a second encoded area including the (N+1)-th to 2N-th bits of the encoded data. The M bits of the original data have an equivalent binary value increased by an incremental step which is P times of an incremental step for the N bits of the first encoded area.

公开(公告)号：US20240194229A1

公开(公告)日：2024-06-13

申请号：US18064303

申请日：2022-12-12

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yun-Yuan WANG ,  Cheng-Hsien LU ,  Po-Hao TSENG ,  Ming-Hsiu LEE

IPC: G11C7/10 ,  G11C7/14 ,  G11C8/08

CPC classification number: G11C7/1069 ,  G11C7/14 ,  G11C8/08

Abstract: The disclosure provides an in-memory search (IMS) memory cell, an IMS method and an IMS memory device. The IMS method comprises: encoding a search data and a storage data by a first IMS encoding into a first IMS encoded search data and a first IMS encoded storage data; encoding the first IMS encoded search data by a second IMS encoding into a plurality of search voltages; encoding the first IMS encoded storage data by the second IMS encoding into a plurality of threshold voltages of a plurality of memory cells of a plurality IMS memory cells of the IMS memory device; and searching the IMS memory cells by the search voltages to generate a search result.

公开(公告)号：US20240021254A1

公开(公告)日：2024-01-18

申请号：US17812243

申请日：2022-07-13

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Po-Hao TSENG ,  Tian-Cih BO

IPC: G11C16/34 ,  G11C16/30 ,  G11C16/26

CPC classification number: G11C16/3404 ,  G11C16/30 ,  G11C16/26

Abstract: A memory device for in-memory search is provided. The memory device includes a plurality of memory cells, and each of the memory cells stores a stored data and receives a search data, including a first transistor and a second transistor. The first transistor has a first threshold voltage and receives a first gate bias. The second transistor is connected to the first transistor, and the second transistor has a second threshold voltage and receives a second gate bias. The stored data is encoded according to the first threshold voltage and the second threshold voltage, and the search data is encoded according to the first gate bias and the second gate bias. There is a mismatch distance between the stored data and the search data. An output current generated by each of the memory cells is related to the mismatch distance.

公开(公告)号：US20240012567A1

公开(公告)日：2024-01-11

申请号：US18069255

申请日：2022-12-21

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Po-Hao TSENG ,  Feng-Min LEE ,  Tian-Cih BO ,  Ming-Hsiu LEE

IPC: G06F3/06

CPC classification number: G06F3/0614 ,  G06F3/0659 ,  G06F3/0673

Abstract: A memory device is provided. The memory device includes channel layers, word lines, memory layers disposed between the channel layers and the word lines, and memory cells defined at cross-points of the channel layers and the word lines. The memory device is configured for performing a first operation for m times and a second operation for n times, and m is equal to or larger than n. In the first operation, a first electric field is produced in a portion of the memory layers. The word lines are configured for producing a second electric field in the second operation in the portion of the memory layers, and a field direction of the second electric field is different from a field direction of the first electric field.

公开(公告)号：US20230420047A1

公开(公告)日：2023-12-28

申请号：US17846304

申请日：2022-06-22

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Po-Hao TSENG ,  Tian-Cih BO ,  Feng-Min LEE

IPC: G11C15/04

CPC classification number: G11C15/04

Abstract: A hybrid type content addressable memory for implementing in-memory-search and an operation method thereof are provided. The CAM includes a plurality of CAM strings and at least one sense amplifier circuit. Each of the CAM strings includes a plurality of CAM cells. The CAM cells store a plurality of existing data. The sense amplifier circuit is connected to the CAM strings. A plurality of search data are inputted to the CAM strings. A plurality of cell matching results obtained from the CAM cells in each of the CAM strings are integrated via an AND operation to obtain a string matching result. The string matching results obtained from the CAM strings are integrated via an OR operation.