Method for manufacturing memory device

    公开(公告)号:US12114514B2

    公开(公告)日:2024-10-08

    申请号:US18519230

    申请日:2023-11-27

    CPC classification number: H10B63/845 H10B61/22 H10B63/34 H10N50/01 H10N70/066

    Abstract: A memory device and a method for manufacturing the memory device are provided. The memory device includes a stack and a plurality of memory strings. The stack is disposed on the substrate, and the stack includes a plurality of conductive layers and a plurality of insulating layers alternately stacked. The memory strings pass through the stack along a first direction, wherein a first memory string in the memory strings includes a first conductive pillar and a second conductive pillar, a channel layer, and a memory structure. The first conductive pillar and the second conductive pillar respectively extend along the first direction and are separated from each other. The channel layer is disposed between the first conductive pillar and the second conductive pillar. The memory structure surrounds the second conductive pillar, and the memory structure includes a resistive memory material.

    Array of pillars located in a uniform pattern

    公开(公告)号:US11424260B2

    公开(公告)日:2022-08-23

    申请号:US17198080

    申请日:2021-03-10

    Abstract: A memory device comprises a stack of conductive layers, and an array of pillars through the stack. Each of the pillars comprises a plurality of series-connected memory cells located in a layout pattern of pillar locations at cross-points between the pillars and the conductive layers. The pillars in the array are arranged in a set of rows of pillars extending in a first direction. First and second source lines are disposed vertically through the pillars of first and second particular rows of pillars. The set of rows of pillars includes a subset of rows of pillars including multiple members disposed between the first source line and the second source line. A source line conductor is disposed beneath and electrically connected to the first source line, the second source line, and the subset of rows of pillars disposed between the first and second source lines.

    3D NOR memory having vertical source and drain structures

    公开(公告)号:US10910393B2

    公开(公告)日:2021-02-02

    申请号:US16394363

    申请日:2019-04-25

    Abstract: A memory device comprises a plurality of stacks of word lines alternating with insulating strips, the stacks being separated by trenches, the word lines extending in a first direction. A plurality of columns of vertical conductive structures is disposed in the trenches between adjacent stacks. Multi-layer films of memory material and channel material are disposed on sidewalls of word lines on at least one side of the trenches between adjacent vertical conductive structures in the plurality of vertical conductive structure, the channel material in ohmic contact with the vertical conductive structures. At locations of vertical conductive structures in the plurality of vertical conductive structures, the sidewalls of the word lines are recessed between insulating strips in the stacks to form recesses on the sidewalls of the word lines to isolate the word lines from vertical conductive structures.

    Self-aligned 3D memory with confined cell

    公开(公告)号:US10593875B2

    公开(公告)日:2020-03-17

    申请号:US16009901

    申请日:2018-06-15

    Abstract: A plurality of memory cells in a cross-point array in which the memory cell stacks in the cross-points include a switch element, a conductive barrier layer, and a memory cell in series, and having sides aligned within the cross-point area of the corresponding cross-point. The memory cells in the stacks include confinement spacers within the cross-point area having outside surfaces on a pair of opposing sides of the stack, and a body of programmable resistance memory material confined between inside surfaces of the spacers.

    Memory device and method for fabricating the same

    公开(公告)号:US10475811B2

    公开(公告)日:2019-11-12

    申请号:US16188397

    申请日:2018-11-13

    Abstract: A memory device memory device includes a multi-layers stack, a charge-trapping layer, a first channel layer and a SSL switch. The multi-layers stack includes a plurality of insulating layers, a plurality of conductive layers alternatively stacked with the insulating layers and at least one first through opening passing through the conductive layers. The charge-trapping layer blankets over a sidewall of the first through opening. The first channel layer is disposed in the first through opening. The SSL switch is disposed on the multi-layers stack and includes a second channel layer, a gate dielectric layer and a gate. The second channel layer is disposed on and electrically contacting to the first channel layer. The gate dielectric layer is disposed on the second channel layer and made of a material other than that for making the charge-trapping layer. The gate is disposed on the gate dielectric layer.

    SELF-ALIGNED DI-SILICON SILICIDE BIT LINE AND SOURCE LINE LANDING PADS IN 3D VERTICAL CHANNEL MEMORY

    公开(公告)号:US20190311907A1

    公开(公告)日:2019-10-10

    申请号:US15949346

    申请日:2018-04-10

    Abstract: A method for manufacturing a memory device comprises forming an initial silicide layer, including depositing and annealing a precursor metal over a layer of silicon material on a top surface of a stack of conductive strips in amounts effective to result in a majority of the initial silicide layer being a mono-silicon silicide of the precursor metal. The method comprises depositing and annealing additional silicon material over the initial silicide layer in amounts effective to result in formation of di-silicon silicide of the precursor metal to form a landing pad on the top surface of the stack of conductive strips, the formation of the di-silicon silicide of the precursor metal consuming mono-silicon silicide of the initial silicide layer so a majority of a silicide of the landing pad is di-silicon silicide.

    Memory device and method for fabricating the same

    公开(公告)号:US10332835B2

    公开(公告)日:2019-06-25

    申请号:US15806551

    申请日:2017-11-08

    Abstract: A memory device includes a semiconductor substrate, a bottom insulating layer disposed on the semiconductor substrate, a first conductive layer which is a selective epitaxial growth layer disposed on the bottom insulating layer; a plurality insulating layers disposed over the bottom insulating layer; a plurality of second conductive layers alternatively stacked the insulating layers and insulated from the first conductive layer; a contact plug passing through the bottom insulating layer and electrically contacting the semiconductor substrate with the first conductive layer; a channel layer disposed on at least one sidewall of at least one first through opening and electrically contact the contact plug, wherein the first through opening passes through the insulating layers, the second conductive layers, so as to expose the contact plug; and a memory layer disposed between the channel layer and the second conductive layers.

    THREE DIMENSIONAL MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME

    公开(公告)号:US20190035802A1

    公开(公告)日:2019-01-31

    申请号:US15664026

    申请日:2017-07-31

    Abstract: A 3D memory device includes a substrate, a multi-layers stack, at least one memory structure and an etching stop structure. The substrate has a trench. The multi-layers stack includes a first extending portion forming a non-straight angle with a bottom surface of the trench and a second extending portion, wherein both of the first extending portion and the second extending portion include a plurality of conductive layers and a plurality of insulating layers alternatively stacked in the trench. The memory structure is formed in the first extending portion. The etching stop structure is at least partially disposed in the second extending portion and has a material identical to that of the memory structure.

    MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE

    公开(公告)号:US20180301465A1

    公开(公告)日:2018-10-18

    申请号:US15489765

    申请日:2017-04-18

    Abstract: A manufacturing method of a semiconductor structure is provided. The manufacturing method of the semiconductor structure includes the following steps: forming a bottom oxide layer; forming a first conductive layer on the bottom oxide layer; forming a stack including alternately arranged second conductive layers and insulating layers on the first conductive layer; forming a first opening having a first cross-sectional width and penetrating through the stack and a portion of the first conductive layer; forming a second opening having a second cross-sectional width and penetrating through the first conductive layer below the first opening for exposing the bottom oxide layer, wherein the second cross-sectional width is smaller than the first cross-sectional width; and forming a memory layer on a sidewall of the first opening and filled in the second opening.

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