公开(公告)号：US20220076959A1

公开(公告)日：2022-03-10

申请号：US17014432

申请日：2020-09-08

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： HUAN-YUNG YEH

IPC: H01L21/308 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/033

Abstract: The present application discloses a method for fabricating a semiconductor device using a tilted etch process. The method for fabricating the semiconductor device includes providing a target layer, forming a first hard mask layer on the target layer, forming second hard mask layers on the first hard mask layer, performing a first tilted etch process on the first hard mask layer to form first openings along the first hard mask layer and adjacent to first sides of the second hard mask layers, and performing a second tilted etch process on the first hard mask layer to form second openings along the first hard mask layer and adjacent to second sides of the second hard mask layers. The first tilted etch process and the second tilted etch process use the second hard mask layers as pattern guides and the first hard mask layer is turned into a patterned first hard mask layer by the first openings and the second openings.

公开(公告)号：US20230268226A1

公开(公告)日：2023-08-24

申请号：US17677008

申请日：2022-02-22

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： HUAN-YUNG YEH ,  CHUN-CHI LAI

IPC: H01L21/768 ,  H01L29/40 ,  H01L21/3213 ,  H01L21/28

CPC classification number: H01L21/76843 ,  H01L29/401 ,  H01L21/32135 ,  H01L21/28079 ,  H01L27/10885

Abstract: A method for fabricating a semiconductor device includes forming a trench extending from a top surface of a semiconductor substrate into the semiconductor substrate, and forming a gate dielectric layer lining the trench. The method also includes forming a gate electrode layer in the trench and over the top surface of the semiconductor substrate, and forming a bit line structure over a S/D region of the semiconductor structure. The bit line structure includes a protection liner having a U-shaped profile and in direct contact with an upper portion of the gate dielectric layer. The formation of the gate electrode layer includes performing a first deposition process, performing a first etching process after the first deposition process, and performing a second deposition process after the first etching process.

公开(公告)号：US20240355674A1

公开(公告)日：2024-10-24

申请号：US18763006

申请日：2024-07-03

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： HUAN-YUNG YEH ,  CHUN-CHI LAI

IPC: H01L21/768 ,  H01L21/28 ,  H01L21/3213 ,  H01L29/40 ,  H10B12/00

CPC classification number: H01L21/76843 ,  H01L21/28079 ,  H01L21/32135 ,  H01L29/401 ,  H10B12/482

Abstract: A method for fabricating a semiconductor device includes forming a trench extending from a top surface of a semiconductor substrate into the semiconductor substrate, and forming a gate dielectric layer lining the trench. The method also includes forming a gate electrode layer in the trench and over the top surface of the semiconductor substrate, and forming a bit line structure over a S/D region of the semiconductor structure. The bit line structure includes a protection liner having a U-shaped profile and in direct contact with an upper portion of the gate dielectric layer. The formation of the gate electrode layer includes performing a first deposition process, performing a first etching process after the first deposition process, and performing a second deposition process after the first etching process.

公开(公告)号：US20220139716A1

公开(公告)日：2022-05-05

申请号：US17572807

申请日：2022-01-11

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： HUAN-YUNG YEH

IPC: H01L21/308 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/033

Abstract: The present application discloses a method for fabricating a semiconductor device using a tilted etch process. The method includes forming an etching stop layer on a substrate, forming a target layer on the etching stop layer, forming a first hard mask layer on the target layer, forming second hard mask layers on the first hard mask layer, performing a first tilted etch process on the first hard mask layer to form first openings along the first hard mask layer and adjacent to first sides of the second hard mask layers, and performing a second tilted etch process on the first hard mask layer to form second openings along the first hard mask layer and adjacent to second sides of the second hard mask layers.

公开(公告)号：US20240047217A1

公开(公告)日：2024-02-08

申请号：US18382214

申请日：2023-10-20

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： HUAN-YUNG YEH

IPC: H01L21/308 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01L21/3088 ,  H01L21/3086 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/32139

Abstract: The present application discloses a semiconductor device including a first isolation structure, a second isolation structure, and a third isolation structure disposed in a semiconductor substrate. The semiconductor device further includes a transistor and a resistor. The transistor is disposed between the first isolation structure and the second isolation structure, and includes a gate electrode and a first source/drain (S/D) region. The resistor is disposed between the second isolation structure and the third isolation structure, and includes a resistor electrode. The first S/D region is disposed between the gate electrode and the second isolation structure, and is electrically connected to the resistor electrode.

公开(公告)号：US20230335408A1

公开(公告)日：2023-10-19

申请号：US18212298

申请日：2023-06-21

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： HUAN-YUNG YEH

IPC: H01L21/308 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01L21/3088 ,  H01L21/3086 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/32139

Abstract: The present application discloses a semiconductor device including a first isolation structure, a second isolation structure, and a third isolation structure disposed in a semiconductor substrate. The semiconductor device further includes a transistor and a resistor. The transistor is disposed between the first isolation structure and the second isolation structure, and includes a gate electrode and a first source/drain (S/D) region. The resistor is disposed between the second isolation structure and the third isolation structure, and includes a resistor electrode. The first S/D region is disposed between the gate electrode and the second isolation structure, and is electrically connected to the resistor electrode.

公开(公告)号：US20210028054A1

公开(公告)日：2021-01-28

申请号：US16520656

申请日：2019-07-24

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： HUAN-YUNG YEH

IPC: H01L21/764 ,  H01L23/532 ,  H01L21/768

Abstract: The present disclosure provides a semiconductor device and a method for forming the semiconductor device. The method includes forming a first conductive structure over a substrate, forming a first dielectric structure over the first conductive structure, transforming a sidewall portion of the first conductive structure into a first dielectric portion, removing the first dielectric portion such that a width of the first dielectric structure is greater than a width of a remaining portion of the first conductive structure, and forming an inter-layer dielectric (ILD) layer covering sidewalls of the first dielectric structure such that a first air spacer is formed between the ILD layer and the remaining portion of the first conductive structure.