公开(公告)号：US12062611B2

公开(公告)日：2024-08-13

申请号：US17665703

申请日：2022-02-07

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tai-I Yang ,  Li-Lin Su ,  Yung-Hsu Wu ,  Hsin-Ping Chen ,  Cheng-Chi Chuang

IPC分类号： H01L23/528 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522

CPC分类号： H01L23/5283 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76898 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/5226

摘要： Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece having an interconnect structure that includes a first conductive feature, a second conductive feature disposed beside the first conductive feature, and an inter-level dielectric disposed between the first conductive feature and the second conductive feature. A conductive material of an etch stop layer is selectively deposited on the first conductive feature and on the second conductive feature without depositing the conductive material on the inter-level dielectric, and the inter-level dielectric is removed to form a gap between the first conductive feature and the second conductive feature.

公开(公告)号：US20200006228A1

公开(公告)日：2020-01-02

申请号：US16380386

申请日：2019-04-10

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tai-I Yang ,  Li-Lin Su ,  Yung-Hsu Wu ,  Hsin-Ping Chen ,  Cheng-Chi Chuang

IPC分类号： H01L23/528 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522

摘要： Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece having an interconnect structure that includes a first conductive feature, a second conductive feature disposed beside the first conductive feature, and an inter-level dielectric disposed between the first conductive feature and the second conductive feature. A conductive material of an etch stop layer is selectively deposited on the first conductive feature and on the second conductive feature without depositing the conductive material on the inter-level dielectric, and the inter-level dielectric is removed to form a gap between the first conductive feature and the second conductive feature.

公开(公告)号：US12080593B2

公开(公告)日：2024-09-03

申请号：US17859981

申请日：2022-07-07

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsin-Ping Chen ,  Ming-Han Lee ,  Shin-Yi Yang ,  Yung-Hsu Wu ,  Chia-Tien Wu ,  Shau-Lin Shue ,  Min Cao

IPC分类号： H01L21/768 ,  H01L21/321 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L21/76846 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76844 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53252 ,  H01L23/53266 ,  H01L21/3212

摘要： Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a second contact feature over the first contact feature, a barrier layer between the second dielectric layer and the second contact feature, and a liner between the barrier layer and the second contact feature. An interface between the first contact feature and the second contact feature includes the liner but is free of the barrier layer.

公开(公告)号：US11860550B2

公开(公告)日：2024-01-02

申请号：US17868398

申请日：2022-07-19

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tai-I Yang ,  Wei-Chen Chu ,  Hsiang-Wei Liu ,  Shau-Lin Shue ,  Li-Lin Su ,  Yung-Hsu Wu

IPC分类号： G03F7/00 ,  H01L21/768 ,  G03F7/004 ,  G03F7/09

CPC分类号： G03F7/70633 ,  G03F7/0035 ,  G03F7/0043 ,  G03F7/0047 ,  G03F7/094 ,  G03F7/70625 ,  H01L21/7682 ,  H01L21/76807 ,  H01L21/76837 ,  H01L21/76885 ,  H01L21/76897 ,  H01L21/76849

摘要： Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.

公开(公告)号：US20230073811A1

公开(公告)日：2023-03-09

申请号：US17984443

申请日：2022-11-10

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsin-Ping Chen ,  Yung-Hsu Wu ,  Chia-Tien Wu ,  Min Cao ,  Ming-Han Lee ,  Shau-Lin Shue ,  Shin-Yi Yang

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522

摘要： Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a second contact feature over the first contact feature, a barrier layer between the second dielectric layer and the second contact feature, and a liner between the barrier layer and the second contact feature. An interface between the first contact feature and the second contact feature includes the liner but is free of the barrier layer.

公开(公告)号：US10714421B2

公开(公告)日：2020-07-14

申请号：US15689784

申请日：2017-08-29

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tai-I Yang ,  Wei-Chen Chu ,  Yung-Hsu Wu ,  Chung-Ju Lee

IPC分类号： H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768

摘要： Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a conductive line over the semiconductor substrate. The semiconductor device structure also includes a conductive via on the conductive line. The conductive via has an upper portion and a protruding portion. The protruding portion extends from a bottom of the upper portion towards the conductive line. The bottom of the upper portion is wider than a top of the upper portion. The semiconductor device structure further includes a dielectric layer over the semiconductor substrate, and the dielectric layer surrounds the conductive line and the conductive via.

公开(公告)号：US10534273B2

公开(公告)日：2020-01-14

申请号：US15586881

申请日：2017-05-04

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tai-I Yang ,  Wei-Chen Chu ,  Hsiang-Wei Liu ,  Shau-Lin Shue ,  Li-Lin Su ,  Yung-Hsu Wu

IPC分类号： G03F7/20 ,  H01L21/768 ,  G03F7/004 ,  G03F7/00 ,  G03F7/09

摘要： Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.

公开(公告)号：US20200006060A1

公开(公告)日：2020-01-02

申请号：US16171436

申请日：2018-10-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shao-Kuan Lee ,  Hsin-Yen Huang ,  Yung-Hsu Wu ,  Cheng-Chin Lee ,  Hai-Ching Chen ,  Shau-Lin Shue

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L23/522

摘要： A structure is provided that includes a first conductive component and a first interlayer dielectric (ILD) that surrounds the first conductive component. A self-assembly layer is formed on the first conductive component but not on the first ILD. A first dielectric layer is formed over the first ILD but not over the first conductive component. A second ILD is formed over the first conductive component and over the first ILD. An opening is etched in the second ILD. The opening is at least partially aligned with the first conductive component. The first dielectric layer protects portions of the first ILD located therebelow from being etched. The opening is filled with a conductive material to form a second conductive component in the opening.

公开(公告)号：US12009202B2

公开(公告)日：2024-06-11

申请号：US17379161

申请日：2021-07-19

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shao-Kuan Lee ,  Hsin-Yen Huang ,  Yung-Hsu Wu ,  Cheng-Chin Lee ,  Hai-Ching Chen ,  Shau-Lin Shue

IPC分类号： H01L23/48 ,  H01L21/02 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L21/02304 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226

摘要： A structure is provided that includes a first conductive component and a first interlayer dielectric (ILD) that surrounds the first conductive component. A self-assembly layer is formed on the first conductive component but not on the first ILD. A first dielectric layer is formed over the first ILD but not over the first conductive component. A second ILD is formed over the first conductive component and over the first ILD. An opening is etched in the second ILD. The opening is at least partially aligned with the first conductive component. The first dielectric layer protects portions of the first ILD located therebelow from being etched. The opening is filled with a conductive material to form a second conductive component in the opening.

公开(公告)号：US20240085803A1

公开(公告)日：2024-03-14

申请号：US18514254

申请日：2023-11-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tai-I Yang ,  Wei-Chen Chu ,  Hsiang-Wei Liu ,  Shau-Lin Shue ,  Li-Lin Su ,  Yung-Hsu Wu

IPC分类号： G03F7/00 ,  G03F7/004 ,  G03F7/09 ,  H01L21/768

CPC分类号： G03F7/70633 ,  G03F7/0035 ,  G03F7/0043 ,  G03F7/0047 ,  G03F7/094 ,  G03F7/70625 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76837 ,  H01L21/76885 ,  H01L21/76897 ,  H01L21/76849

摘要： Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.