公开(公告)号：US20240347625A1

公开(公告)日：2024-10-17

申请号：US18752172

申请日：2024-06-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Chi Chuang ,  Lin-Yu Huang ,  Chia-Hao Chang ,  Yu-Ming Lin ,  Ting-Ya Lo ,  Chi-Lin Teng ,  Hsin-Yen Huang ,  Hai-Ching Chen

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L21/823468 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor structure includes a substrate, a semiconductor layer, a gate stack, two first gate spacers over two opposing sidewalls of the gate stack and extending above the gate stack; a second gate spacer over a sidewall of one of the first gate spacers and having an upper portion over a lower portion; an etch stop layer adjacent to the lower portion and spaced away from the upper portion; and a seal layer over the gate stack, the two first gate spacers and the second gate spacer, resulting in a first void and a second void below the first seal layer. The first void is above the lower portion of the second gate spacer and laterally between the etch stop layer and the upper portion of the second gate spacer. The second void is above the gate stack and laterally between the two first gate spacers.

公开(公告)号：US20240258166A1

公开(公告)日：2024-08-01

申请号：US18608673

申请日：2024-03-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yen Huang ,  Shao-Kuan Lee ,  Cheng-Chin Lee ,  Hai-Ching Chen ,  Shau-Lin Shue

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76879 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53295

Abstract: Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece that includes a substrate and an interconnect structure. The interconnect structure includes a first conductive feature disposed within a first inter-level dielectric layer. A blocking layer is selectively formed on the first conductive feature without forming the blocking layer on the first inter-level dielectric layer. An alignment feature is selectively formed on the first inter-level dielectric layer without forming the alignment feature on the blocking layer. The blocking layer is removed from the first conductive feature, and a second inter-level dielectric layer is formed on the alignment feature and on the first conductive feature. The second inter-level dielectric layer is patterned to define a recess for a second conductive feature, and the second conductive feature is formed within the recess.

公开(公告)号：US12027606B2

公开(公告)日：2024-07-02

申请号：US17717684

申请日：2022-04-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Chi Chuang ,  Lin-Yu Huang ,  Chia-Hao Chang ,  Yu-Ming Lin ,  Ting-Ya Lo ,  Chi-Lin Teng ,  Hsin-Yen Huang ,  Hai-Ching Chen

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L21/823468 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor structure includes a substrate, a semiconductor layer, a gate stack, two first gate spacers over two opposing sidewalls of the gate stack and extending above the gate stack; a second gate spacer over a sidewall of one of the first gate spacers and having an upper portion over a lower portion; an etch stop layer adjacent to the lower portion and spaced away from the upper portion; and a seal layer over the gate stack, the two first gate spacers and the second gate spacer, resulting in a first void and a second void below the first seal layer. The first void is above the lower portion of the second gate spacer and laterally between the etch stop layer and the upper portion of the second gate spacer. The second void is above the gate stack and laterally between the two first gate spacers.

公开(公告)号：US12009202B2

公开(公告)日：2024-06-11

申请号：US17379161

申请日：2021-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-Kuan Lee ,  Hsin-Yen Huang ,  Yung-Hsu Wu ,  Cheng-Chin Lee ,  Hai-Ching Chen ,  Shau-Lin Shue

IPC: H01L23/48 ,  H01L21/02 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L21/02304 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226

Abstract: A structure is provided that includes a first conductive component and a first interlayer dielectric (ILD) that surrounds the first conductive component. A self-assembly layer is formed on the first conductive component but not on the first ILD. A first dielectric layer is formed over the first ILD but not over the first conductive component. A second ILD is formed over the first conductive component and over the first ILD. An opening is etched in the second ILD. The opening is at least partially aligned with the first conductive component. The first dielectric layer protects portions of the first ILD located therebelow from being etched. The opening is filled with a conductive material to form a second conductive component in the opening.

公开(公告)号：US11710700B2

公开(公告)日：2023-07-25

申请号：US17391216

申请日：2021-08-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Yi Yang ,  Yu-Chen Chan ,  Ming-Han Lee ,  Hai-Ching Chen ,  Shau-Lin Shue

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/53276 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53295

Abstract: A semiconductor structure is provided. The semiconductor structure comprises a first conductive feature embedded within a first dielectric layer, a via disposed over the first conductive feature, a second conductive feature disposed over the via, and a graphene layer disposed over at least a portion of the first conductive feature. The via electrically couples the first conductive feature to the second conductive feature.

公开(公告)号：US11690228B2

公开(公告)日：2023-06-27

申请号：US17184892

申请日：2021-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Song-Fu Liao ,  Rainer Yen-Chieh Huang ,  Hai-Ching Chen ,  Chung-Te Lin

IPC: H01L21/02 ,  H10B51/30 ,  H01L21/768 ,  H10B53/30

CPC classification number: H10B51/30 ,  H01L21/76876 ,  H10B53/30

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first conductive structure arranged over a substrate. A memory layer is arranged over the first conductive structure, below a second conductive structure, and includes a ferroelectric material. An annealed seed layer is arranged between the first and second conductive structures and directly on a first side of the memory layer. An amount of the crystal structure that includes an orthorhombic phase is greater than about 35 percent.

公开(公告)号：US11640924B2

公开(公告)日：2023-05-02

申请号：US17314877

申请日：2021-05-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I Yang ,  Yu-Chieh Liao ,  Chia-Tien Wu ,  Hsin-Ping Chen ,  Hai-Ching Chen ,  Shau-Lin Shue

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/3213 ,  H01L23/532 ,  H01L23/522 ,  H01L21/3105

Abstract: The present disclosure provides a method of forming an integrated circuit structure. The method includes depositing a first metal layer on a semiconductor substrate; forming a hard mask on the first metal layer; patterning the first metal layer to form first metal features using the hard mask as an etch mask; depositing a dielectric layer of a first dielectric material on the first metal features and in gaps among the first metal features; performing a chemical mechanical polishing (CMP) process to both the dielectric layer and the hard mask; removing the hard mask, thereby having portions of the dielectric layer extruded above the metal features; forming an inter-layer dielectric (ILD) layer of the second dielectric material different from the first dielectric material; and patterning the ILD layer to form openings that expose the first metal features and are constrained to be self-aligned with the first metal features by the extruded portions of the first dielectric layer.

公开(公告)号：US11508755B2

公开(公告)日：2022-11-22

申请号：US17184856

申请日：2021-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Rainer Yen-Chieh Huang ,  Hai-Ching Chen ,  Chung-Te Lin

IPC: H01L27/11 ,  H01L29/51 ,  H01L29/78 ,  H01L27/1159 ,  H01L29/66 ,  H01L21/28

Abstract: The present disclosure relates to an integrated circuit (IC) in which a memory structure comprises a ferroelectric structure without critical-thickness limitations. The memory structure comprises a first electrode and the ferroelectric structure. The ferroelectric structure is vertically stacked with the first electrode and comprises a first ferroelectric layer, a second ferroelectric layer, and a first restoration layer. The second ferroelectric layer overlies the first ferroelectric layer, and the first restoration layer is between and borders the first and second ferroelectric layers. The first restoration layer is a different material type than that of the first and second ferroelectric layers and is configured to decouple crystalline lattices of the first and second ferroelectric layers so the first and second ferroelectric layers do not reach critical thicknesses. A critical thickness corresponds to a thickness at and above which the orthorhombic phase becomes thermodynamically unstable, such that remanent polarization is lost.

公开(公告)号：US20220254794A1

公开(公告)日：2022-08-11

申请号：US17168361

申请日：2021-02-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Rainer Yen-Chieh Huang ,  Hai-Ching Chen ,  Chung-Te Lin

IPC: H01L27/1159 ,  H01L23/522 ,  H01L29/51 ,  H01L29/78 ,  H01L29/66

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a gate electrode over a substrate, and a gate dielectric layer arranged over the gate electrode. The gate dielectric layer includes a ferroelectric material. An active structure is arranged over the gate dielectric layer and includes a semiconductor material. A source contact and a drain contact are arranged over the active structure. A capping structure is arranged between the source and drain contacts and over the active structure. The capping structure includes a first metal material.

公开(公告)号：US20220238693A1

公开(公告)日：2022-07-28

申请号：US17717684

申请日：2022-04-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Chi Chuang ,  Lin-Yu Huang ,  Chia-Hao Chang ,  Yu-Ming Lin ,  Ting-Ya Lo ,  Chi-Lin Teng ,  Hsin-Yen Huang ,  Hai-Ching Chen

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/78 ,  H01L21/8234

Abstract: A semiconductor structure includes a substrate, a semiconductor layer, a gate stack, two first gate spacers over two opposing sidewalls of the gate stack and extending above the gate stack; a second gate spacer over a sidewall of one of the first gate spacers and having an upper portion over a lower portion; an etch stop layer adjacent to the lower portion and spaced away from the upper portion; and a seal layer over the gate stack, the two first gate spacers and the second gate spacer, resulting in a first void and a second void below the first seal layer. The first void is above the lower portion of the second gate spacer and laterally between the etch stop layer and the upper portion of the second gate spacer. The second void is above the gate stack and laterally between the two first gate spacers.