公开(公告)号：US10957580B2

公开(公告)日：2021-03-23

申请号：US16983475

申请日：2020-08-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Wei Liu ,  Chia-Tien Wu ,  Wei-Chen Chu

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3115

Abstract: A method includes forming a hard mask over a target layer, performing a treatment on a first portion of the hard mask to form a treated portion, with a second portion of the hard mask left untreated as an untreated portion. The method further includes subjecting both the treated portion and the untreated portion of the hard mask to etching, in which the untreated portion is removed as a result of the etching, and the treated portion remains after the etching. A layer underlying the hard mask is etched, and the treated portion of the hard mask is used as a part of an etching mask in the etching.

公开(公告)号：US10784155B2

公开(公告)日：2020-09-22

申请号：US16657485

申请日：2019-10-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Chen Chu ,  Tai-I Yang ,  Cheng-Chi Chuang ,  Chia-Tien Wu

IPC: H01L21/768 ,  H01L21/311

Abstract: The present disclosure describes methods which employ a patterning photolithography/etch operations to form self-aligned interconnects with multi-metal gap fill. For example, the method includes a first pattern structure and a second pattern structure formed over a dielectric layer. Each of the first and second pattern structures includes a pair of spacers, and a center portion between the pair of spacers. A first opening, self-aligned to a space between the first and second pattern structures, is formed in the dielectric layer. A first conductive material is deposited in the first opening. The center portion of the second pattern structure is removed to form a void above the dielectric layer and between the pair of spacers of the second pattern structure. A second opening, self-aligned to the void, is formed in the dielectric layer; and a second conductive material is deposited in the second opening.

公开(公告)号：US20200051853A1

公开(公告)日：2020-02-13

申请号：US16657485

申请日：2019-10-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Chen Chu ,  Tai-I Yang ,  Cheng-Chi Chuang ,  Chia-Tien Wu

IPC: H01L21/768 ,  H01L21/311

Abstract: The present disclosure describes methods which employ a patterning photolithography/etch operations to form self-aligned interconnects with multi-metal gap fill. For example, the method includes a first pattern structure and a second pattern structure formed over a dielectric layer. Each of the first and second pattern structures includes a pair of spacers, and a center portion between the pair of spacers. A first opening, self-aligned to a space between the first and second pattern structures, is formed in the dielectric layer. A first conductive material is deposited in the first opening. The center portion of the second pattern structure is removed to form a void above the dielectric layer and between the pair of spacers of the second pattern structure. A second opening, self-aligned to the void, is formed in the dielectric layer; and a second conductive material is deposited in the second opening.

公开(公告)号：US10483159B2

公开(公告)日：2019-11-19

申请号：US16010007

申请日：2018-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Chen Chu ,  Tai-I Yang ,  Cheng-Chi Chuang ,  Chia-Tien Wu

IPC: H01L21/768 ,  H01L21/311 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532

Abstract: The present disclosure describes methods which employ a patterning photolithography/etch operations to form self-aligned interconnects with multi-metal gap fill. For example, the method includes a first pattern structure and a second pattern structure formed over a dielectric layer. Each of the first and second pattern structures includes a pair of spacers, and a center portion between the pair of spacers. A first opening, self-aligned to a space between the first and second pattern structures, is formed in the dielectric layer. A first conductive material is deposited in the first opening. The center portion of the second pattern structure is removed to form a void above the dielectric layer and between the pair of spacers of the second pattern structure. A second opening, self-aligned to the void, is formed in the dielectric layer; and a second conductive material is deposited in the second opening.

公开(公告)号：US20180308798A1

公开(公告)日：2018-10-25

申请号：US16022131

申请日：2018-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Tien Wu ,  Hsiang-Wei Liu ,  Wei-Chen Chu

IPC: H01L23/535 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/535 ,  H01L21/76832 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/528

Abstract: A first metal layer of a semiconductor device includes a plurality of first metal lines that each extend along a first axis, and a first rail structure that extends along the first axis. The first rail structure is physically separated from the first metal lines. A second metal layer is located over the first metal layer. The second metal layer includes a plurality of second metal lines that each extend along a second axis orthogonal to the first axis, and a second rail structure that extends along the first axis. The second rail structure is physically separated from the second metal lines. The second rail structure is located directly over the first rail structure. A plurality of vias is located between the first metal layer and the second metal layer. A subset of the vias electrically interconnects the first rail structure to the second rail structure.

公开(公告)号：US10026647B2

公开(公告)日：2018-07-17

申请号：US15498259

申请日：2017-04-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Chen Chu ,  Tai-I Yang ,  Cheng-Chi Chuang ,  Chia-Tien Wu

IPC: H01L21/768 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76816 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76813

Abstract: The present disclosure describes methods which employ a patterning photolithography/etch operations to form self-aligned interconnects with multi-metal gap fill. For example, the method includes a first pattern structure and a second pattern structure formed over a dielectric layer. Each of the first and second pattern structures includes a pair of spacers, and a center portion between the pair of spacers. A first opening, self-aligned to a space between the first and second pattern structures, is formed in the dielectric layer. A first conductive material is deposited in the first opening. The center portion of the second pattern structure is removed to form a void above the dielectric layer and between the pair of spacers of the second pattern structure. A second opening, self-aligned to the void, is formed in the dielectric layer; and a second conductive material is deposited in the second opening.

公开(公告)号：US20180108611A1

公开(公告)日：2018-04-19

申请号：US15294286

申请日：2016-10-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Tien Wu ,  Hsiang-Wei Liu ,  Wei-Chen Chu

IPC: H01L23/535 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L21/76832 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/528

Abstract: A first metal layer of a semiconductor device includes a plurality of first metal lines that each extend along a first axis, and a first rail structure that extends along the first axis. The first rail structure is physically separated from the first metal lines. A second metal layer is located over the first metal layer. The second metal layer includes a plurality of second metal lines that each extend along a second axis orthogonal to the first axis, and a second rail structure that extends along the first axis. The second rail structure is physically separated from the second metal lines. The second rail structure is located directly over the first rail structure. A plurality of vias is located between the first metal layer and the second metal layer. A subset of the vias electrically interconnects the first rail structure to the second rail structure.

公开(公告)号：US11682618B2

公开(公告)日：2023-06-20

申请号：US17212113

申请日：2021-03-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pokuan Ho ,  Chia-Tien Wu ,  Hsin-Ping Chen ,  Wei-Chen Chu

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/528

Abstract: The present disclosure relates to an integrated chip that includes a substrate, a first metal line, and a hybrid metal line. The first metal line includes a first metal material and is within a first interlayer dielectric (ILD) layer over the substrate. The hybrid metal line is also within the first ILD layer. The hybrid metal line includes a pair of first metal segments that comprise the first metal material. The hybrid metal line further includes a second metal segment that comprises a second metal material that is different from the first metal material. The second metal segment is laterally between the pair of first metal segments.

公开(公告)号：US20220350262A1

公开(公告)日：2022-11-03

申请号：US17868398

申请日：2022-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I YANG ,  Wei-Chen Chu ,  Hsiang-Wei Liu ,  Shau-Lin Shue ,  Li-Lin Su ,  Yung-Hsu Wu

IPC: G03F7/20 ,  H01L21/768 ,  G03F7/004 ,  G03F7/00 ,  G03F7/09

Abstract: Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.

公开(公告)号：US20220310508A1

公开(公告)日：2022-09-29

申请号：US17212113

申请日：2021-03-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pokuan Ho ,  Chia-Tien Wu ,  Hsin-Ping Chen ,  Wei-Chen Chu

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768

Abstract: The present disclosure relates to an integrated chip that includes a substrate, a first metal line, and a hybrid metal line. The first metal line includes a first metal material and is within a first interlayer dielectric (ILD) layer over the substrate. The hybrid metal line is also within the first ILD layer. The hybrid metal line includes a pair of first metal segments that comprise the first metal material. The hybrid metal line further includes a second metal segment that comprises a second metal material that is different from the first metal material. The second metal segment is laterally between the pair of first metal segments.