-
公开(公告)号：US20240363409A1
公开(公告)日：2024-10-31
申请号：US18771313
申请日：2024-07-12
发明人： Yu-Sheng Wang , Chi-Cheng Hung , Chen-Yuan Kao , Yi-Wei Chiu , Liang-Yueh Ou Yang , Yueh-Ching Pai
IPC分类号： H01L21/768 , H01L21/285 , H01L21/288 , H01L23/485 , H01L29/417 , H01L29/66 , H01L29/78
CPC分类号： H01L21/76895 , H01L21/2885 , H01L21/76829 , H01L21/76831 , H01L21/7684 , H01L21/76849 , H01L21/76874 , H01L21/76877 , H01L21/76879 , H01L21/76883 , H01L29/41775 , H01L29/66477 , H01L29/665 , H01L29/66553 , H01L29/78 , H01L29/7833 , H01L21/28518 , H01L21/76843 , H01L21/76855 , H01L21/76873 , H01L23/485
摘要： A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a source/drain region of the transistor or a gate electrode in the gate stack is exposed through the contact opening. A conductive capping layer is formed to extend into the contact opening. A metal-containing material is plated on the conductive capping layer in a plating solution using electrochemical plating. The metal-containing material has a portion filling the contact opening. The plating solution has a sulfur content lower than about 100 ppm. A planarization is performed on the wafer to remove excess portions of the metal-containing material. A remaining portion of the metal-containing material and a remaining portion of the conductive capping layer in combination form a contact plug.
-
公开(公告)号：US12021147B2
公开(公告)日：2024-06-25
申请号：US18064350
申请日：2022-12-12
IPC分类号： H01L21/768 , H01L29/49 , H01L29/66 , H01L29/78 , H01L29/51
CPC分类号： H01L29/7851 , H01L29/4966 , H01L29/66545 , H01L29/66795 , H01L29/513 , H01L29/517 , H01L29/665
摘要： A method includes forming a first semiconductor fin protruding from a substrate and forming a gate stack over the first semiconductor fin. Forming the gate stack includes depositing a gate dielectric layer over the first semiconductor fin, depositing a first seed layer over the gate dielectric layer, depositing a second seed layer over the first seed layer, wherein the second seed layer has a different structure than the first seed layer, and depositing a conductive layer over the second seed layer, wherein the first seed layer, the second seed layer, and the conductive layer include the same conductive material. The method also includes forming source and drain regions adjacent the gate stack.
-
公开(公告)号：US11616132B2
公开(公告)日：2023-03-28
申请号：US17340802
申请日：2021-06-07
发明人： Yu-Sheng Wang , Chi-Cheng Hung , Chia-Ching Lee , Ching-Hwanq Su
IPC分类号： H01L27/092 , H01L29/66 , H01L29/49 , H01L29/78 , H01L21/28 , H01L21/762 , H01L29/06 , H01L29/08 , H01L29/51
摘要： A semiconductor device and method of manufacturing are provided. In an embodiment a first nucleation layer is formed within an opening for a gate-last process. The first nucleation layer is treated in order to remove undesired oxygen by exposing the first nucleation layer to a precursor that reacts with the oxygen to form a gas. A second nucleation layer is then formed, and a remainder of the opening is filled with a bulk conductive material.
-
公开(公告)号：US20140264707A1
公开(公告)日：2014-09-18
申请号：US14291076
申请日：2014-05-30
发明人： En-Ting Lee , Kun-El Chen , Yu-Sheng Wang , Chien-Chung Chen , Huai-Tei Yang
IPC分类号： H01L31/0352 , H01L27/146
CPC分类号： H01L31/0352 , H01L21/26513 , H01L27/1446 , H01L27/1464 , H01L27/14643 , H01L27/14687
摘要： The present disclosure relates to a back-side illuminated CMOS image sensor (BSI CIS). In some embodiments, the BSI CSI has a semiconductor substrate with a front-side and a back-side. A plurality of photodetectors are located within the front-side of the semiconductor substrate. An implantation region is located within the semiconductor substrate at a position separated from the plurality of photodetectors. The implantation region is disposed below the plurality of photodetectors and has a non-uniform doping concentration along a lateral plane parallel to the back-side of the semiconductor substrate. The non-uniform doping concentration allows for the BSI CSI to achieve a small total thickness variation (TTV) between one or more photodetectors and a back-side of a thinned semiconductor substrate that provides for good device performance.
摘要翻译： 本公开涉及背面照明CMOS图像传感器（BSI CIS）。 在一些实施例中，BSI CSI具有前侧和后侧的半导体衬底。 多个光电探测器位于半导体衬底的前侧内。 注入区域位于与多个光电检测器分离的位置内的半导体衬底内。 注入区域设置在多个光电检测器的下方，并且沿着平行于半导体衬底的背面的横向平面具有不均匀的掺杂浓度。 不均匀掺杂浓度允许BSI CSI在一个或多个光电检测器与减薄的半导体衬底的背面之间实现小的总厚度变化（TTV），从而提供良好的器件性能。
-
公开(公告)号：US20210043521A1
公开(公告)日：2021-02-11
申请号：US17068041
申请日：2020-10-12
发明人： Ya-Wen Chiu , Da-Yuan Lee , Hsien-Ming Lee , Kai-Cyuan Yang , Yu-Sheng Wang , Chih-Hsiang Fan , Kun-Wa Kuok
IPC分类号： H01L21/8238 , H01L29/49 , H01L29/78 , H01L27/092 , H01L29/66 , H01L29/51
摘要： A method includes forming a first transistor, which includes forming a first gate dielectric layer over a first channel region in a substrate and forming a first work-function layer over the first gate dielectric layer, wherein forming the first work-function layer includes depositing a work-function material using first process conditions to form the work-function material having a first proportion of different crystalline orientations and forming a second transistor, which includes forming a second gate dielectric layer over a second channel region in the substrate and forming a second work-function layer over the second gate dielectric layer, wherein forming the second work-function layer includes depositing the work-function material using second process conditions to form the work-function material having a second proportion of different crystalline orientations.
-
公开(公告)号：US20190067443A1
公开(公告)日：2019-02-28
申请号：US16176214
申请日：2018-10-31
发明人： Chi-Cheng Hung , Yu-Sheng Wang , Weng-Cheng Chen , Hao-Han Wei , Ming-Ching Chung , Chi-Cherng Jeng
IPC分类号： H01L29/51 , H01L29/78 , H01L29/49 , H01L21/28 , H01L21/8238 , H01L21/285 , H01L29/40
摘要： A method of fabricating tantalum nitride barrier layer in an ultra low threshold voltage semiconductor device is provided. The method includes forming a high-k dielectric layer over a semiconductor substrate. Subsequently, a tantalum nitride barrier layer is formed on the high-k dielectric layer. The tantalum nitride barrier layer has a Ta:N ratio between 1.2 and 3. Next, a plurality of first metal gates is formed on the tantalum nitride barrier layer. The first metal gates are patterned, and then a second metal gate is formed on the tantalum nitride barrier layer.
-
公开(公告)号：US09991362B2
公开(公告)日：2018-06-05
申请号：US15281296
申请日：2016-09-30
发明人： Yu-Sheng Wang , Chi-Cheng Hung , Chia-Ching Lee , Chung-Chiang Wu
IPC分类号： H01L29/66 , H01L29/49 , H01L21/285
CPC分类号： H01L29/66545 , H01L21/28556 , H01L29/4966 , H01L29/785
摘要： In a method of manufacturing a tungsten layer by an atomic layer deposition, a seed layer on an underlying layer is formed on a substrate by supplying a boron containing gas and a dilute gas, and a tungsten layer is formed on the seed layer by supplying a tungsten containing gas. A flow ratio of a flow amount of the boron containing gas to a total flow amount of the boron containing gas and the dilute gas is in a range from 1/21 to 1/4.
-
公开(公告)号：US09947753B2
公开(公告)日：2018-04-17
申请号：US14842680
申请日：2015-09-01
发明人： Chi-Cheng Hung , Kei-Wei Chen , Yu-Sheng Wang , Ming-Ching Chung , Chia-Yang Wu
IPC分类号： H01L29/417 , H01L29/66 , H01L29/78 , H01L21/768 , H01L29/08 , H01L29/165 , H01L21/285 , H01L23/485 , H01L29/49
CPC分类号： H01L29/41725 , H01L21/28518 , H01L21/76805 , H01L21/76831 , H01L21/76843 , H01L21/76855 , H01L23/485 , H01L29/0847 , H01L29/165 , H01L29/4966 , H01L29/66545 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A semiconductor structure includes a semiconductor substrate, at least one dielectric layer, a dielectric spacer liner (DSL) layer, and at least one conductor. The dielectric layer is present on the semiconductor substrate. The dielectric layer has at least one contact hole exposing at least a portion of the semiconductor substrate. The semiconductor substrate has at least one recess communicating with the contact hole. The recess has a bottom surface and at least one sidewall. The DSL layer is present on at least the sidewall of the recess. The conductor is present at least partially in the contact hole and is electrically connected to the semiconductor substrate.
-
公开(公告)号：US09870995B2
公开(公告)日：2018-01-16
申请号：US14743926
申请日：2015-06-18
发明人： Jun-Nan Nian , Shiu-Ko Jangjian , Chi-Cheng Hung , Yu-Sheng Wang , Hung-Hsu Chen
IPC分类号： H01L23/532 , B32B15/01 , H01L21/288 , H01L21/768 , B32B15/20
CPC分类号： H01L23/53238 , B32B15/01 , H01L21/2885 , H01L21/76877
摘要： A copper layer structure includes a first copper layer, a second copper layer and a carbon-rich copper layer. The second copper layer is disposed over the first copper layer. The carbon-rich copper layer is sandwiched between the first copper layer and the second copper layer. A carbon concentration of the carbon-rich copper layer is greater than a carbon concentration of the first copper layer and a carbon concentration of the second copper layer.
-
公开(公告)号：US09837507B1
公开(公告)日：2017-12-05
申请号：US15281305
申请日：2016-09-30
发明人： Yu-Sheng Wang , Chi-Cheng Hung , Da-Yuan Lee , Hsin-Yi Lee , Kuan-Ting Liu
CPC分类号： H01L29/66545 , H01L29/4966 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： A field effect transistor includes a channel layer made of a semiconductor and a metal gate structure. The metal gate structure includes a gate dielectric layer, a barrier layer formed on the gate dielectric layer, a work function adjustment layer formed on the barrier layer and made of one of Al and TiAl, a blocking layer formed on the work function adjustment layer and made of TiN, and a body metal layer formed on the blocking layer and made of W. A gate length over the channel layer is in a range from 5 nm to 15 nm, and a thickness of the first conductive layer is in a range of 0.2 nm to 3.0 nm. A range between a largest thickness and a smallest thickness of the first conductive layer is more than 0% and less than 10% of an average thickness of the first conductive layer.
-
-
-
-
-
-
-
-
-
搜索结果
32 条记录 (耗时 0.021 秒)
