公开(公告)号：US11742404B2

公开(公告)日：2023-08-29

申请号：US17169892

申请日：2021-02-08

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Chun Chieh Wang ,  Yueh-Ching Pai

IPC分类号： H01L29/423 ,  H01L29/417 ,  H01L29/49 ,  H01L21/28 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L21/285 ,  H01L21/8234

CPC分类号： H01L29/42376 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/28518 ,  H01L21/823437 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

摘要： In a method of manufacturing a semiconductor device, a gate space is formed by removing a sacrificial gate electrode, a gate dielectric layer is formed in the gate space, conductive layers are formed on the gate dielectric layer to fully fill the gate space, the gate dielectric layer and the conducive layers are recessed to form a recessed gate electrode, and a contact metal layer is formed on the recessed gate electrode. The recessed gate electrode does not includes tungsten, and the contact metal layer includes tungsten.

公开(公告)号：US20210257254A1

公开(公告)日：2021-08-19

申请号：US17234136

申请日：2021-04-19

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Sheng Wang ,  Chi-Cheng Hung ,  Chen-Yuan Kao ,  Yi-Wei Chiu ,  Liang-Yueh Ou Yang ,  Yueh-Ching Pai

IPC分类号： H01L21/768 ,  H01L29/417 ,  H01L29/78 ,  H01L21/288 ,  H01L29/66

摘要： A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a source/drain region of the transistor or a gate electrode in the gate stack is exposed through the contact opening. A conductive capping layer is formed to extend into the contact opening. A metal-containing material is plated on the conductive capping layer in a plating solution using electrochemical plating. The metal-containing material has a portion filling the contact opening. The plating solution has a sulfur content lower than about 100 ppm. A planarization is performed on the wafer to remove excess portions of the metal-containing material. A remaining portion of the metal-containing material and a remaining portion of the conductive capping layer in combination form a contact plug.

公开(公告)号：US10937910B2

公开(公告)日：2021-03-02

申请号：US16654175

申请日：2019-10-16

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chun-Chieh Wang ,  Yu-Ting Lin ,  Yueh-Ching Pai ,  Shih-Chieh Chang ,  Huai-Tei Yang

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L27/088 ,  H01L21/8238 ,  H01L21/768 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/32 ,  H01L21/8234 ,  H01L21/02

摘要： A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure formed over a fin structure and a gate spacer formed on a sidewall surface of the gate structure. The semiconductor structure also includes a first source/drain (S/D) epitaxial layer formed in the fin structure and adjacent to the gate spacer, and a second S/D epitaxial layer formed over the first S/D epitaxial layer. A top surface of the second S/D layer is higher than a top surface of the first S/D epitaxial layer.

公开(公告)号：US12068197B2

公开(公告)日：2024-08-20

申请号：US17234136

申请日：2021-04-19

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Sheng Wang ,  Chi-Cheng Hung ,  Chen-Yuan Kao ,  Yi-Wei Chiu ,  Liang-Yueh Ou Yang ,  Yueh-Ching Pai

IPC分类号： H01L21/768 ,  H01L21/288 ,  H01L23/485 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/285

CPC分类号： H01L21/76895 ,  H01L21/2885 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76849 ,  H01L21/76874 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883 ,  H01L29/41775 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66553 ,  H01L29/78 ,  H01L29/7833 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76873 ,  H01L23/485

摘要： A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a source/drain region of the transistor or a gate electrode in the gate stack is exposed through the contact opening. A conductive capping layer is formed to extend into the contact opening. A metal-containing material is plated on the conductive capping layer in a plating solution using electrochemical plating. The metal-containing material has a portion filling the contact opening. The plating solution has a sulfur content lower than about 100 ppm. A planarization is performed on the wafer to remove excess portions of the metal-containing material. A remaining portion of the metal-containing material and a remaining portion of the conductive capping layer in combination form a contact plug.

公开(公告)号：US11545363B2

公开(公告)日：2023-01-03

申请号：US17128408

申请日：2020-12-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Po-Yu Lin ,  Chi-Yu Chou ,  Hsien-Ming Lee ,  Huai-Tei Yang ,  Chun-Chieh Wang ,  Yueh-Ching Pai ,  Chi-Jen Yang ,  Tsung-Ta Tang ,  Yi-Ting Wang

IPC分类号： H01L21/28 ,  H01L29/49 ,  H01L21/3213 ,  H01L21/285

摘要： The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.

公开(公告)号：US10971602B2

公开(公告)日：2021-04-06

申请号：US16852819

申请日：2020-04-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chien-Shun Liao ,  Huai-Tei Yang ,  Chun Chieh Wang ,  Yueh-Ching Pai ,  Chun-I Wu

IPC分类号： H01L21/28 ,  H01L29/49 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/51 ,  H01L29/66

摘要： An embodiment is a method of semiconductor processing. The method includes depositing a high-k gate dielectric layer over a semiconductor fin. A barrier layer is deposited over the high-k gate dielectric layer. A silicon passivation layer is deposited over the barrier layer. A nitrogen treatment is performed on the silicon passivation layer. A capping layer is deposited over the silicon passivation layer. The capping layer is annealed.

公开(公告)号：US20200251574A1

公开(公告)日：2020-08-06

申请号：US16852819

申请日：2020-04-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chien-Shun Liao ,  Huai-Tei Yang ,  Chun-Chieh Wang ,  Yueh-Ching Pai ,  Chun-I Wu

IPC分类号： H01L29/66 ,  H01L21/28 ,  H01L29/49 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/51

摘要： An embodiment is a method of semiconductor processing. The method includes depositing a high-k gate dielectric layer over a semiconductor fin. A barrier layer is deposited over the high-k gate dielectric layer. A silicon passivation layer is deposited over the barrier layer. A nitrogen treatment is performed on the silicon passivation layer. A capping layer is deposited over the silicon passivation layer. The capping layer is annealed.

公开(公告)号：US20230387328A1

公开(公告)日：2023-11-30

申请号：US18446918

申请日：2023-08-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chunchieh Wang ,  Yueh-Ching Pai

IPC分类号： H01L29/786 ,  H01L29/06 ,  H01L21/02 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC分类号： H01L29/78696 ,  H01L29/0673 ,  H01L21/02603 ,  H01L21/0228 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

摘要： An embodiment includes a device having a first set of nanostructures on a substrate, the first set of nanostructures including a first channel region, a second set of nanostructures on the substrate, the second set of nanostructures including a second channel region, a gate dielectric layer wrapping around each of the first and second sets of nanostructures, a first work function tuning layer on the gate dielectric layer of the first set of nanostructures, the first work function tuning layer wrapping around each of the first set of nanostructures, a glue layer on the first work function tuning layer, the glue layer wrapping around each of the first set of nanostructures, a second work function tuning layer on the glue layer of the first set of nanostructures and on the gate dielectric layer of the second set of nanostructures, and a fill layer on the second work function tuning layer.

公开(公告)号：US20220278197A1

公开(公告)日：2022-09-01

申请号：US17314752

申请日：2021-05-07

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chunchieh Wang ,  Yueh-Ching Pai

IPC分类号： H01L29/06 ,  H01L21/02

摘要： An embodiment includes a device having a first set of nanostructures on a substrate, the first set of nanostructures including a first channel region, a second set of nanostructures on the substrate, the second set of nanostructures including a second channel region, a gate dielectric layer wrapping around each of the first and second sets of nanostructures, a first work function tuning layer on the gate dielectric layer of the first set of nanostructures, the first work function tuning layer wrapping around each of the first set of nanostructures, a glue layer on the first work function tuning layer, the glue layer wrapping around each of the first set of nanostructures, a second work function tuning layer on the glue layer of the first set of nanostructures and on the gate dielectric layer of the second set of nanostructures, and a fill layer on the second work function tuning layer.

公开(公告)号：US20210036147A1

公开(公告)日：2021-02-04

申请号：US16888846

申请日：2020-05-31

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chun-Chieh Wang ,  Sheng-Wei Yeh ,  Yueh-Ching Pai ,  Chi-Jen Yang

IPC分类号： H01L29/78 ,  H01L29/16 ,  H01L29/66 ,  H01L21/768

摘要： Provided are a gate structure and a method of forming the same. The gate structure includes a gate dielectric layer, a metal layer, and a cluster layer. The metal layer is disposed over the gate dielectric layer. The cluster layer is sandwiched between the metal layer and the gate dielectric layer, wherein the cluster layer at least includes an amorphous silicon layer, an amorphous carbon layer, or an amorphous germanium layer. In addition, a semiconductor device including the gate structure is provided.