公开(公告)号：US10964590B2

公开(公告)日：2021-03-30

申请号：US15967056

申请日：2018-04-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tien-Pei Chou ,  Ken-Yu Chang ,  Sheng-Hsuan Lin ,  Yueh-Ching Pai ,  Yu-Ting Lin

IPC: H01L21/768 ,  H01L21/285 ,  H01L23/52 ,  H01L29/40

Abstract: The present disclosure describes a method to a metallization process with improved gap fill properties. The method includes forming a contact opening in an oxide, forming a barrier layer in the contact opening, forming a liner layer on the barrier layer, and forming a first metal layer on the liner layer to partially fill the contact opening. The method further includes forming a second metal layer on the first metal layer to fill the contact opening, where forming the second metal layer includes sputter depositing the second metal layer with a first radio frequency (RF) power and a direct current power, as well as reflowing the second metal layer with a second RF power.

公开(公告)号：US20200343087A1

公开(公告)日：2020-10-29

申请号：US16927638

申请日：2020-07-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Ting Lin ,  Chen-Yuan Kao ,  Rueijer Lin ,  Yu-Sheng Wang ,  I-Li Chen ,  Hong-Ming Wu

IPC: H01L21/02 ,  H01L29/51 ,  H01L21/768 ,  H01L21/285 ,  H01L29/417

Abstract: The present disclosure describes a method that includes forming a dielectric layer over a contact region on a substrate; etching the dielectric layer to form a contact opening to expose the contact region; and pre-cleaning the exposed contact region to remove a residual material formed by the etching. During the pre-cleaning, the contact region is exposed to an inductively coupled radio frequency (RF) plasma. Also, during the pre-cleaning, a direct current power supply unit (DC PSU) provides a bias voltage to the substrate and a magnetic field is applied to the inductively coupled RF plasma to collimate ions.

公开(公告)号：US10804097B2

公开(公告)日：2020-10-13

申请号：US16568720

申请日：2019-09-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Wei Chang ,  Min-Hsiu Hung ,  Hung-Yi Huang ,  Chun Chieh Wang ,  Yu-Ting Lin

IPC: H01L21/02 ,  H01L21/762 ,  H01L23/532 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/285 ,  H01L21/8234

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.

公开(公告)号：US12191199B2

公开(公告)日：2025-01-07

申请号：US17216444

申请日：2021-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tien-Pei Chou ,  Ken-Yu Chang ,  Sheng-Hsuan Lin ,  Yueh-Ching Pai ,  Yu-Ting Lin

IPC: H01L21/768 ,  H01L21/285 ,  H01L23/52 ,  H01L29/40

Abstract: The present disclosure describes a method to a metallization process with improved gap fill properties. The method includes forming a contact opening in an oxide, forming a barrier layer in the contact opening, forming a liner layer on the barrier layer, and forming a first metal layer on the liner layer to partially fill the contact opening. The method further includes forming a second metal layer on the first metal layer to fill the contact opening, where forming the second metal layer includes sputter depositing the second metal layer with a first radio frequency (RF) power and a direct current power, as well as reflowing the second metal layer with a second RF power.

公开(公告)号：US11295956B2

公开(公告)日：2022-04-05

申请号：US16887218

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Wei Chang ,  Kao-Feng Lin ,  Min-Hsiu Hung ,  Yi-Hsiang Chao ,  Huang-Yi Huang ,  Yu-Ting Lin

IPC: H01L21/285 ,  H01L21/28 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49

Abstract: The present disclosure relates to a method for fabricating a semiconductor structure. The method includes providing a substrate with a gate structure, an insulating structure over the gate structure, and a S/D region; depositing a titanium silicide layer over the S/D region with a first chemical vapor deposition (CVD) process. The first CVD process includes a first hydrogen gas flow. The method also includes depositing a titanium nitride layer over the insulating structure with a second CVD process. The second CVD process includes a second hydrogen gas flow. The first and second CVD processes are performed in a single reaction chamber and a flow rate of the first hydrogen gas flow is higher than a flow rate of the second hydrogen gas flow.

公开(公告)号：US11232945B2

公开(公告)日：2022-01-25

申请号：US17036734

申请日：2020-09-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Wei Chang ,  Min-Hsiu Hung ,  Hung-Yi Huang ,  Chun Chieh Wang ,  Yu-Ting Lin

IPC: H01L21/762 ,  H01L21/02 ,  H01L23/532 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/285 ,  H01L21/8234

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.

公开(公告)号：US10714334B2

公开(公告)日：2020-07-14

申请号：US15860354

申请日：2018-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Wei Chang ,  Huang-Yi Huang ,  Chun-chieh Wang ,  Yu-Ting Lin ,  Min-Hsiu Hung

IPC: H01L21/762 ,  H01L21/02 ,  H01L23/532 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/285 ,  H01L21/8234

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.

公开(公告)号：US10714329B2

公开(公告)日：2020-07-14

申请号：US16146529

申请日：2018-09-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Ting Lin ,  Chen-Yuan Kao ,  Rueijer Lin ,  Yu-Sheng Wang ,  I-Li Chen ,  Hong-Ming Wu

IPC: H01L21/4763 ,  H01L21/02 ,  H01L29/51 ,  H01L21/768 ,  H01L21/285 ,  H01L29/417

Abstract: The present disclosure describes a method that includes forming a dielectric layer over a contact region on a substrate; etching the dielectric layer to form a contact opening to expose the contact region; and pre-cleaning the exposed contact region to remove a residual material formed by the etching. During the pre-cleaning, the first contact region is exposed to an inductively coupled radio frequency (RF) plasma. Also, during the pre-cleaning, a direct current power supply unit (DC PSU) provides a bias voltage to the substrate and a magnetic field is applied to the inductively coupled RF plasma to collimate ions.

公开(公告)号：US09893185B2

公开(公告)日：2018-02-13

申请号：US15054133

申请日：2016-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ta Wu ,  Yu-Ting Lin ,  Po-Kai Hsiao ,  Po-Kang Ho ,  Ting-Chun Wang

IPC: H01L29/76 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/7848 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/165 ,  H01L29/66545

Abstract: A FinFET including a substrate, a plurality of isolation structures, a plurality of blocking layers, and a gate stack is provided. The substrate has a plurality of semiconductor fins. The isolation structures are located on the substrate to isolate the semiconductor fins. In addition, the semiconductor fins protrude from the isolation structures. The blocking layers are located between the isolation structures and the semiconductor fins. The material of the blocking layers is different from the material of the isolation structures. The gate stack is disposed across portions of the semiconductor fins, portions of the blocking layers and portions of the isolation structures. In addition, a method for fabricating the FinFET is also provided.

公开(公告)号：US20220230884A1

公开(公告)日：2022-07-21

申请号：US17712480

申请日：2022-04-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Wei Chang ,  Kao-Feng Lin ,  Min-Hsiu Hung ,  Yi-Hsiang Chao ,  Huang-Yi Huang ,  Yu-Ting Lin

IPC: H01L21/285 ,  H01L21/28 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49

Abstract: The present disclosure relates to a method for fabricating a semiconductor structure. The method includes providing a substrate with a gate structure, an insulating structure over the gate structure, and a S/D region; depositing a titanium silicide layer over the S/D region with a first chemical vapor deposition (CVD) process. The first CVD process includes a first hydrogen gas flow. The method also includes depositing a titanium nitride layer over the insulating structure with a second CVD process. The second CVD process includes a second hydrogen gas flow. The first and second CVD processes are performed in a single reaction chamber and a flow rate of the first hydrogen gas flow is higher than a flow rate of the second hydrogen gas flow.