公开(公告)号：US11329160B2

公开(公告)日：2022-05-10

申请号：US15435168

申请日：2017-02-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ta Wu ,  Shiu-Ko Jangjian ,  Chung-Ren Sun ,  Ming-Te Chen ,  Ting-Chun Wang ,  Jun-Jie Cheng

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/66

Abstract: A semiconductor device includes a semiconductor fin, a lining oxide layer, a silicon nitride based layer and a gate oxide layer. The semiconductor fin has a top fin surface, an upper fin side surface portion adjacent to the top fin surface, and a lower fin side surface contiguously connected to the upper fin side surface portion. The lining oxide layer peripherally encloses the lower fin side surface portion of the semiconductor fin. The silicon nitride based layer is disposed conformally over the lining oxide layer. The gate oxide layer is disposed conformally over the top fin surface and the upper fin side surface portion.

公开(公告)号：US11015260B2

公开(公告)日：2021-05-25

申请号：US16698528

申请日：2019-11-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jun-Nan Nian ,  Shiu-Ko Jangjian ,  Yu-Ren Peng ,  Yao-Hsiang Liang ,  Ting-Chun Wang

IPC: C25D17/00 ,  C25D21/12 ,  C25D3/38 ,  H01L21/768

Abstract: A method for performing an electrochemical plating (ECP) process includes contacting a surface of a substrate with a plating solution comprising ions of a metal to be deposited, electroplating the metal on the surface of the substrate, in situ monitoring a plating current flowing through the plating solution between an anode and the substrate immersed in the plating solution as the ECP process continues, and adjusting a composition of the plating solution in response to the plating current being below a critical plating current such that voids formed in a subset of conductive lines having a highest line-end density among a plurality of conductive lines for a metallization layer over the substrate are prevented.

公开(公告)号：US20210125935A1

公开(公告)日：2021-04-29

申请号：US17140654

申请日：2021-01-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Yang Wu ,  Shiu-Ko JangJian ,  Ting-Chun Wang ,  Yung-Si Yu

IPC: H01L23/532 ,  H01L29/417 ,  H01L21/768 ,  H01L21/3213

Abstract: A semiconductor device includes a transistor having a source/drain and a gate. The semiconductor device also includes a conductive contact for the transistor. The conductive contact provides electrical connectivity to the source/drain or the gate of the transistor. The conductive contact includes a plurality of barrier layers. The barrier layers have different depths from one another.

公开(公告)号：US10192988B2

公开(公告)日：2019-01-29

申请号：US15660355

申请日：2017-07-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ta Wu ,  Shiu-Ko Jangjian ,  Cheng-Wei Chen ,  Ting-Chun Wang

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66

Abstract: Operations in fabricating a Fin FET include providing a substrate having a fin structure, where an upper portion of the fin structure has a first fin surface profile. An isolation region is formed on the substrate and in contact with the fin structure. A portion of the isolation region is recessed by an etch process to form a recessed portion and to expose the upper portion of the fin structure, where the recessed portion has a first isolation surface profile. A thermal hydrogen treatment is applied to the fin structure and the recessed portion. A gate dielectric layer is formed with a substantially uniform thickness over the fin structure, where the recessed portion is adjusted from the first isolation surface profile to a second isolation surface profile and the fin structure is adjusted from the first fin surface profile to a second fin surface profile by the thermal hydrogen treatment.

公开(公告)号：US09893185B2

公开(公告)日：2018-02-13

申请号：US15054133

申请日：2016-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ta Wu ,  Yu-Ting Lin ,  Po-Kai Hsiao ,  Po-Kang Ho ,  Ting-Chun Wang

IPC: H01L29/76 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/7848 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/165 ,  H01L29/66545

Abstract: A FinFET including a substrate, a plurality of isolation structures, a plurality of blocking layers, and a gate stack is provided. The substrate has a plurality of semiconductor fins. The isolation structures are located on the substrate to isolate the semiconductor fins. In addition, the semiconductor fins protrude from the isolation structures. The blocking layers are located between the isolation structures and the semiconductor fins. The material of the blocking layers is different from the material of the isolation structures. The gate stack is disposed across portions of the semiconductor fins, portions of the blocking layers and portions of the isolation structures. In addition, a method for fabricating the FinFET is also provided.

公开(公告)号：US20170250280A1

公开(公告)日：2017-08-31

申请号：US15054086

申请日：2016-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ta Wu ,  Yung-Yu Wang ,  Yung-Hsiang Chan ,  Chia-Ying Tsai ,  Ting-Chun Wang

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/02

CPC classification number: H01L29/7848 ,  H01L21/02236 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/785

Abstract: A fin-type field effect transistor comprising a substrate, at least one gate structure, spacers and strained source and drain regions is described. The at least one gate structure is disposed over the substrate and on the isolation structures. The spacers are disposed on sidewalls of the at least one gate structure. First blocking material layers are disposed on the spacers. The strained source and drain regions are disposed at two opposite sides of the at least one gate structure. Second blocking material layers are disposed on the strained source and drain regions. The first and second blocking material layers comprise oxygen-rich oxide materials.

公开(公告)号：US09666692B2

公开(公告)日：2017-05-30

申请号：US14815547

申请日：2015-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ta Wu ,  Ting-Chun Wang ,  Yuan-Nien Chen

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3115 ,  H01L29/78 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L29/785 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/3115 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device includes a semiconductor fin, a first silicon nitride based layer, a lining oxide layer, a second silicon nitride based layer and a gate oxide layer. The semiconductor fin has a top surface, a first side surface adjacent to the top surface, and a second side surface which is disposed under and adjacent to the first side surface. The first silicon nitride based layer peripherally encloses the second side surface of the semiconductor fin. The lining oxide layer is disposed conformal to the first silicon nitride based layer. The second silicon nitride based layer is disposed conformal to the lining oxide layer. The gate oxide layer is disposed conformal to the top surface and the first side surface of the semiconductor fin.

公开(公告)号：US09577102B1

公开(公告)日：2017-02-21

申请号：US14865663

申请日：2015-09-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Ting Hsiao ,  Cheng-Ta Wu ,  Lun-Kuang Tan ,  Liang-Yu Yen ,  Ting-Chun Wang ,  Tsung-Han Wu ,  Wei-Ming You

IPC: H01L21/28 ,  H01L29/78 ,  H01L29/66 ,  H01L21/3215 ,  H01L29/06

CPC classification number: H01L29/7856 ,  H01L21/3215 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method of forming a gate includes: forming a dummy gate; forming an inter layer dielectric (ILD) laterally adjacent to the dummy gate; doping a dopant into the dummy gate and the ILD, in which a surface dopant concentration of the dummy gate is lower than a surface dopant concentration of the ILD; removing the dummy gate to form a cavity after doping the dopant into the dummy gate and the ILD; and forming the gate in the cavity.

Abstract translation: 一种形成栅极的方法包括：形成一个虚拟栅极; 形成横向邻近所述虚拟栅极的层间电介质（ILD）; 将掺杂剂掺杂到伪栅极和ILD中，其中伪栅极的表面掺杂剂浓度低于ILD的表面掺杂剂浓度; 在将掺杂剂掺杂到虚拟栅极和ILD中之后去除伪栅极以形成空腔; 并在腔中形成门。

公开(公告)号：US09064823B2

公开(公告)日：2015-06-23

申请号：US13889515

申请日：2013-05-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Che Huang ,  Pu-Fang Chen ,  Ting-Chun Wang

IPC: G06F17/50 ,  H01L21/322 ,  C30B15/00 ,  C03B15/14 ,  C30B23/00 ,  H01L21/66 ,  C30B29/06

CPC classification number: H01L21/3225 ,  C30B29/06 ,  H01L21/324 ,  H01L22/12 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method is provided for qualifying a semiconductor wafer for subsequent processing, such as thermal processing. A plurality of locations are defined about a periphery of the semiconductor wafer, and one or more properties, such as oxygen concentration and a density of bulk micro defects present, are measured at each of the plurality of locations. A statistical profile associated with the periphery of the semiconductor wafer is determined based on the one or more properties measured at the plurality of locations. The semiconductor wafer is subsequently thermally treated when the statistical profile falls within a predetermined range. The semiconductor wafer is rejected from subsequent processing when the statistical profile deviates from the predetermined range. As such, wafers prone to distortion, warpage, and breakage are rejected from subsequent thermal processing.

Abstract translation: 提供了一种用于限定半导体晶片以进行后续处理（诸如热处理）的方法。 围绕半导体晶片的周边限定多个位置，并且在多个位置的每一个处测量一个或多个特性，例如存在的氧浓度和体积微缺陷的密度。 基于在多个位置处测量的一个或多个属性来确定与半导体晶片的外围相关联的统计概况。 当统计特性落在预定范围内时，半导体晶片随后进行热处理。 当统计概况偏离预定范围时，半导体晶片从后续处理中被拒绝。 因此，容易发生变形，翘曲和断裂的晶片从随后的热处理中被拒绝。

公开(公告)号：US11598016B2

公开(公告)日：2023-03-07

申请号：US17507382

申请日：2021-10-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jun-Nan Nian ,  Shiu-Ko Jangjian ,  Ting-Chun Wang ,  Ing-Ju Lee

IPC: C25D7/12 ,  C25D3/38 ,  C25D21/12 ,  H01L21/768 ,  C25D17/00

Abstract: An electrochemical plating (ECP) system is provided. The ECP system includes an ECP cell comprising a plating solution for an ECP process, a sensor configured to in situ measure an interface resistance between a plated metal and an electrolyte in the plating solution as the ECP process continues, a plating solution supply system in fluid communication with the ECP cell and configured to supply the plating solution to the ECP cell, and a control system operably coupled to the ECP cell, the sensor and the plating solution supply system. The control system is configured to compare the interface resistance with a threshold resistance and to adjust a composition of the plating solution in response to the interface resistance being below the threshold resistance.