公开(公告)号：US20210125935A1

公开(公告)日：2021-04-29

申请号：US17140654

申请日：2021-01-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Yang Wu ,  Shiu-Ko JangJian ,  Ting-Chun Wang ,  Yung-Si Yu

IPC: H01L23/532 ,  H01L29/417 ,  H01L21/768 ,  H01L21/3213

Abstract: A semiconductor device includes a transistor having a source/drain and a gate. The semiconductor device also includes a conductive contact for the transistor. The conductive contact provides electrical connectivity to the source/drain or the gate of the transistor. The conductive contact includes a plurality of barrier layers. The barrier layers have different depths from one another.

公开(公告)号：US20170250281A1

公开(公告)日：2017-08-31

申请号：US15054089

申请日：2016-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Hsiung Tsai ,  Ziwei Fang ,  Shiu-Ko JangJian ,  Kei-Wei Chen ,  Huai-Tei Yang ,  Ying-Lang Wang

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/66 ,  H01L29/161 ,  H01L27/12 ,  H01L21/8234

CPC classification number: H01L29/7848 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L27/1211 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A fin-type field effect transistor comprising a substrate, at least one gate structure, first spacers, second spacers and source and drain regions is described. The substrate has fins and insulators disposed between the fins. The at least one gate structure is disposed over the fins and disposed on the insulators. The first spacers are disposed on opposite sidewalls of the at least one gate structure. The source and drain regions are disposed on two opposite sides of the at least one gate structure and beside the first spacers. The second spacers are disposed on the two opposite sides of the at least one gate structure and beside the first spacers. The source and drain regions are sandwiched between the opposite second spacers.

公开(公告)号：US09721883B1

公开(公告)日：2017-08-01

申请号：US15060612

申请日：2016-03-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Lung Lai ,  Chen-Chieh Chiang ,  Chi-Cherng Jeng ,  Shiu-Ko JangJian

IPC: H01L23/52 ,  H01L23/522 ,  H01L23/528 ,  H01L21/683 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/187 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/528 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2221/68381

Abstract: Integrated circuits and manufacturing methods of the same are disclosed. The integrated circuit includes a transistor, a first dielectric layer, an etch stop layer, a first via and a first conductive layer. The first dielectric layer is disposed between the transistor and the etch stop layer. The first via is disposed in the first dielectric layer and the etch stop layer, and electrically connected to the transistor. The first conductive layer is in contact with the first via, wherein the first via is disposed between the first conductive layer and the transistor, and the etch stop layer is aside a portion of the first via adjacent to the first conductive layer.

公开(公告)号：US11942419B2

公开(公告)日：2024-03-26

申请号：US17809914

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shiu-Ko JangJian ,  Tsung-Hsuan Hong ,  Chun Che Lin ,  Chih-Nan Wu

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L21/76849 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit structure includes a dielectric layer and an etch stop layer. The etch stop layer includes a first sub layer including a metal nitride over the first dielectric layer, and a second sub layer overlying or underlying the first sub layer. The second sub layer includes a metal compound comprising an element selected from carbon and oxygen, and is in contact with the first sub layer.

公开(公告)号：US10886226B2

公开(公告)日：2021-01-05

申请号：US16050191

申请日：2018-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Yang Wu ,  Shiu-Ko JangJian ,  Ting-Chun Wang ,  Yung-Si Yu

IPC: H01L23/532 ,  H01L29/417 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/311

Abstract: A semiconductor device includes a transistor having a source/drain and a gate. The semiconductor device also includes a conductive contact for the transistor. The conductive contact provides electrical connectivity to the source/drain or the gate of the transistor. The conductive contact includes a plurality of barrier layers. The barrier layers have different depths from one another.

公开(公告)号：US10573749B2

公开(公告)日：2020-02-25

申请号：US15054089

申请日：2016-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Hsiung Tsai ,  Ziwei Fang ,  Shiu-Ko JangJian ,  Kei-Wei Chen ,  Huai-Tei Yang ,  Ying-Lang Wang

IPC: H01L27/01 ,  H01L29/78 ,  H01L27/12 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165

Abstract: A fin-type field effect transistor comprising a substrate, at least one gate structure, first spacers, second spacers and source and drain regions is described. The substrate has fins and insulators disposed between the fins. The at least one gate structure is disposed over the fins and disposed on the insulators. The first spacers are disposed on opposite sidewalls of the at least one gate structure. The source and drain regions are disposed on two opposite sides of the at least one gate structure and beside the first spacers. The second spacers are disposed on the two opposite sides of the at least one gate structure and beside the first spacers. The source and drain regions are sandwiched between the opposite second spacers.

公开(公告)号：US20140167197A1

公开(公告)日：2014-06-19

申请号：US13718688

申请日：2012-12-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shiu-Ko JangJian ,  Chi-Cherng Jeng ,  Volume Chien ,  Ying-Lang Wang

IPC: H01L31/0216 ,  H01L31/18

CPC classification number: H01L27/14687 ,  H01L27/1462 ,  H01L27/14623 ,  H01L27/1463 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14685 ,  H01L31/18

Abstract: A backside illumination image sensor structure comprises an image sensor formed adjacent to a first side of a semiconductor substrate, wherein an interconnect layer is formed over the first side of the semiconductor substrate, a backside illumination film formed over a second side of the semiconductor substrate, a metal shielding layer formed over the backside illumination film and a via embedded in the backside illumination film and coupled between the metal shielding layer and the semiconductor substrate.

Abstract translation: 背面照明图像传感器结构包括与半导体衬底的第一侧相邻形成的图像传感器，其中在所述半导体衬底的第一侧上形成有互连层，形成在所述半导体衬底的第二侧上的背面照明膜， 形成在背面照明膜上的金属屏蔽层和嵌入在背面照明膜中并且连接在金属屏蔽层和半导体基板之间的通孔。

公开(公告)号：US20220336348A1

公开(公告)日：2022-10-20

申请号：US17809914

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shiu-Ko JangJian ,  Tsung-Hsuan Hong ,  Chun Che Lin ,  Chih-Nan Wu

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: An integrated circuit structure includes a dielectric layer and an etch stop layer. The etch stop layer includes a first sub layer including a metal nitride over the first dielectric layer, and a second sub layer overlying or underlying the first sub layer. The second sub layer includes a metal compound comprising an element selected from carbon and oxygen, and is in contact with the first sub layer.

公开(公告)号：US20200350244A1

公开(公告)日：2020-11-05

申请号：US16933551

申请日：2020-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shiu-Ko JangJian ,  Tsung-Hsuan Hong ,  Chun Che Lin ,  Chih-Nan Wu

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: An integrated circuit structure includes a dielectric layer and an etch stop layer. The etch stop layer includes a first sub layer including a metal nitride over the first dielectric layer, and a second sub layer overlying or underlying the first sub layer. The second sub layer includes a metal compound comprising an element selected from carbon and oxygen, and is in contact with the first sub layer.

公开(公告)号：US09691766B1

公开(公告)日：2017-06-27

申请号：US15088117

申请日：2016-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jia-Ming Lin ,  Chun Che Lin ,  Shiu-Ko JangJian ,  Wei Ken Lin ,  Kuang Yao Lo

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3115 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31155 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66803

Abstract: A fin field effect transistor (FinFET) including a substrate, a plurality of insulators, and a gate stack is provided. The substrate includes a plurality of trenches and at least one semiconductor fin between the trenches. The insulators are disposed in the trenches and include doped regions distributed therein. The gate stack partially covers the at least one semiconductor fin and the insulators. A method for fabricating the aforesaid FinFET is also discussed.