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公开(公告)号：US11855146B2
公开(公告)日：2023-12-26
申请号：US17648156
申请日：2022-01-17
发明人： Su-Hao Liu , Wen-Yen Chen , Li-Heng Chen , Li-Ting Wang , Liang-Yin Chen , Huicheng Chang , Yee-Chia Yeo , Ying-Lang Wang
IPC分类号： H01L29/08 , H01L29/66 , H01L29/78 , H01L29/161 , H01L27/092 , H01L21/8238 , H01L21/02 , H01L21/265 , H01L21/285 , H01L21/768 , H01L21/8234 , H01L21/324
CPC分类号： H01L29/0847 , H01L21/02532 , H01L21/26506 , H01L21/28518 , H01L21/324 , H01L21/76814 , H01L21/823418 , H01L21/823431 , H01L21/823814 , H01L21/823821 , H01L21/823828 , H01L27/0924 , H01L29/161 , H01L29/66507 , H01L29/66545 , H01L29/66795 , H01L29/785 , H01L29/7845 , H01L29/7848 , H01L29/7851 , H01L2029/7858
摘要： A method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. At least a portion of the semiconductor region is molten during the melt anneal.
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公开(公告)号：US10516048B2
公开(公告)日：2019-12-24
申请号：US15804887
申请日：2017-11-06
发明人： I-Chih Chen , Ying-Lang Wang , Chih-Mu Huang , Ying-Hao Chen , Wen-Chang Kuo , Jung-Chi Jeng
IPC分类号： H01L29/78 , H01L29/167 , H01L29/08 , H01L29/66 , H01L29/165
摘要： A method of fabricating a semiconductor device includes following steps. A trench is formed in a substrate. A barrier layer and an epitaxy layer are formed in sequence in the trench. The barrier layer has a first dopant. A source/drain recess cavity is formed by etching at least the epitaxial layer. A source/drain region is formed in the source/drain recess cavity. The source/drain region has a second dopant.
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公开(公告)号：US10096672B2
公开(公告)日：2018-10-09
申请号：US15651751
申请日：2017-07-17
发明人： I-Chih Chen , Chih-Mu Huang , Fu-Tsun Tsai , Meng-Yi Wu , Yung-Fa Lee , Ying-Lang Wang
IPC分类号： H01L21/425 , H01L21/02 , H01L29/06 , H01L29/78
摘要： A semiconductor device includes a semiconductor substrate having a first conductivity type region including a first conductivity type impurity. A first gate structure is on the semiconductor substrate overlying the first conductivity type region. A second conductivity type region including a second conductivity type impurity is formed in the semiconductor substrate. A barrier layer is located between the first conductivity type region and the second conductivity type region. The barrier layer prevents diffusion of the second conductivity type impurity from the second conductivity type region into the first conductivity type region.
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公开(公告)号：US09728511B2
公开(公告)日：2017-08-08
申请号：US14109162
申请日：2013-12-17
发明人： Hsi-Jung Wu , Volume Chien , Ying-Lang Wang , Hsin-Chi Chen , Ying-Hao Chen , Hung-Ta Huang
IPC分类号： H01L23/544 , H01L23/00 , H01L23/58 , H01L21/784
CPC分类号： H01L23/562 , H01L21/784 , H01L23/585 , H01L2924/0002 , H01L2924/14 , H01L2924/00
摘要： A semiconductor wafer includes a substrate, an integrated circuit and a die seal ring structure. The substrate is with a die region, a die seal ring region surrounding the die region and a scribe line region surrounding the die seal ring region. The substrate includes a first surface and a second surface opposite to the first surface, and periodic recesses within the first surface of the die seal ring region, the scribe line region or both the die seal ring region and the scribe line region. The integrated circuit is located on the first surface and the second surface of the die region. The die seal ring structure is located on the second surface of the die seal ring region. A semiconductor die is also provided.
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公开(公告)号：US09224691B2
公开(公告)日：2015-12-29
申请号：US13961908
申请日：2013-08-08
IPC分类号： H01L23/532 , H01L23/485 , H01L21/285 , H01L21/768
CPC分类号： H01L23/53266 , H01L21/2855 , H01L21/76805 , H01L21/76814 , H01L21/76846 , H01L23/485 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor contact structures extend through a dielectric material and provide contact to multiple different subjacent materials including a silicide material and a non-silicide material such as doped silicon. The contact structures includes a lower composite layer formed using a multi-step ionized metal plasma (IMP) deposition operation. A lower IMP film is formed at a high AC bias power followed by the formation of an upper IMP film at a lower AC bias power. The composite layer may be formed of titanium. A further layer is formed as a liner over the composite layer and the liner layer may advantageously be formed using CVD and may be TiN. A conductive plug material such as tungsten or copper fills the contact openings.
摘要翻译： 半导体接触结构延伸穿过电介质材料并且提供与包括硅化物材料和非硅化物材料（例如掺杂硅）的多个不同的下层材料的接触。 接触结构包括使用多步电离金属等离子体（IMP）沉积操作形成的下复合层。 下部IMP膜以高AC偏压功率形成，随后以较低的AC偏压功率形成上部IMP膜。 复合层可以由钛形成。 在复合层上形成另一层作为衬垫，并且衬垫层可以有利地使用CVD形成，并且可以是TiN。 诸如钨或铜的导电插塞材料填充接触开口。
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公开(公告)号：US20150170985A1
公开(公告)日：2015-06-18
申请号：US14109162
申请日：2013-12-17
发明人： Hsi-Jung Wu , Volume Chien , Ying-Lang Wang , Hsin-Chi Chen , Ying-Hao Chen , Hung-Ta Huang
IPC分类号： H01L23/10 , H01L23/544 , H01L23/00
CPC分类号： H01L23/562 , H01L21/784 , H01L23/585 , H01L2924/0002 , H01L2924/14 , H01L2924/00
摘要： A semiconductor wafer includes a substrate, an integrated circuit and a die seal ring structure. The substrate is with a die region, a die seal ring region surrounding the die region and a scribe line region surrounding the die seal ring region. The substrate includes a first surface and a second surface opposite to the first surface, and periodic recesses within the first surface of the die seal ring region, the scribe line region or both the die seal ring region and the scribe line region. The integrated circuit is located on the first surface and the second surface of the die region. The die seal ring structure is located on the second surface of the die seal ring region. A semiconductor die is also provided.
摘要翻译： 半导体晶片包括基板，集成电路和模具密封环结构。 基板具有模具区域，围绕模具区域的模具密封环区域和围绕模具密封环区域的划线区域。 基板包括与第一表面相对的第一表面和第二表面，以及在模具密封环区域的第一表面，划线区域或模具密封环区域和划线区域内的周期性凹槽。 集成电路位于模具区域的第一表面和第二表面上。 模具密封环结构位于模具密封环区域的第二表面上。 还提供半导体管芯。
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公开(公告)号：US20230317519A1
公开(公告)日：2023-10-05
申请号：US18330466
申请日：2023-06-07
发明人： Li-Chieh Wu , Tang-Kuei Chang , Kuo-Hsiu Wei , Kei-Wei Chen , Ying-Lang Wang , Su-Hao Liu , Kuo-Ju Chen , Liang-Yin Chen , Huicheng Chang , Ting-Kui Chang , Chia Hsuan Lee
IPC分类号： H01L21/768 , H01L23/522
CPC分类号： H01L21/76883 , H01L21/76825 , H01L23/5226 , H01L29/66795
摘要： The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.
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公开(公告)号：US11329221B2
公开(公告)日：2022-05-10
申请号：US16693946
申请日：2019-11-25
发明人： Wen-Ting Chu , Tong-Chern Ong , Ying-Lang Wang
摘要： The present disclosure, in some embodiments, relates to a method of forming a resistive random access memory (RRAM) device. The method includes forming one or more bottom electrode films over a lower interconnect layer within a lower inter-level dielectric layer. A data storage film having a variable resistance is formed above the one or more bottom electrode films. A lower top electrode film including a metal is over the data storage film, one or more oxygen barrier films are over the lower top electrode film, and an upper top electrode film including a metal nitride is formed over the one or more oxygen barrier films. The one or more oxygen barrier films include one or more of a metal oxide film and a metal oxynitride film. The upper top electrode film is formed to be completely confined over a top surface of the one or more oxygen barrier films.
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公开(公告)号：US20220140079A1
公开(公告)日：2022-05-05
申请号：US17648156
申请日：2022-01-17
发明人： Su-Hao Liu , Wen-Yen Chen , Li-Heng Chen , Li-Ting Wang , Liang-Yin Chen , Huicheng Chang , Yee-Chia Yeo , Ying-Lang Wang
IPC分类号： H01L29/08 , H01L29/66 , H01L29/78 , H01L29/161 , H01L27/092 , H01L21/8238 , H01L21/02 , H01L21/265 , H01L21/285
摘要： A method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. At least a portion of the semiconductor region is molten during the melt anneal.
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10.发明授权公开(公告)号：US10510891B1
公开(公告)日：2019-12-17
申请号：US16504670
申请日：2019-07-08
发明人： Su-Hao Liu , Kuo-Ju Chen , Chun-Hung Wu , Chia-Cheng Chen , Liang-Yin Chen , Huicheng Chang , Ying-Lang Wang
IPC分类号： H01L21/3115 , H01L21/02 , H01L29/78 , H01L27/088 , H01L29/66 , H01L21/3215 , H01L21/8234 , H01L29/165
摘要： Embodiments disclosed herein relate generally to forming an ultra-shallow junction having high dopant concentration and low contact resistance in a p-type source/drain region. In an embodiment, a method includes forming a source/drain region in an active area on a substrate, the source/drain region comprising germanium, performing an ion implantation process using gallium (Ga) to form an amorphous region in the source/drain region, performing an ion implantation process using a dopant into the amorphous region, and subjecting the amorphous region to a thermal process.
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