公开(公告)号：US20220238729A1

公开(公告)日：2022-07-28

申请号：US17159289

申请日：2021-01-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Sung-Hsin Yang ,  Jung-Chi Jeng ,  Ru-Shang Hsiao

IPC分类号： H01L29/94 ,  H01L27/06 ,  H01L29/78 ,  H01L29/66

摘要： Various embodiments of the present disclosure are directed towards a FinFET MOS capacitor. In some embodiments, the FinFET MOS capacitor comprises a substrate and a capacitor fin structure extending upwardly from an upper surface of the substrate. The capacitor fin structure comprises a pair of dummy source/drain regions separated by a dummy channel region and a capacitor gate structure straddling on the capacitor fin structure. The capacitor gate structure is separated from the capacitor fin structure by a capacitor gate dielectric.

公开(公告)号：US10510671B2

公开(公告)日：2019-12-17

申请号：US15884760

申请日：2018-01-31

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chi-Cherng Jeng ,  Shyh-Wei Cheng ,  Yun Chang ,  Chen-Chieh Chiang ,  Jung-Chi Jeng

IPC分类号： H01L23/538 ,  H01L21/50 ,  H01L21/762 ,  H01L21/768 ,  H01L23/00 ,  H01L23/522 ,  H01L23/48

摘要： A method for forming a semiconductor device structure is provided. The method includes forming a first mask layer over a dielectric layer. The first mask layer has a trench. The trench has an inner wall and a bottom surface. The method includes forming a second mask layer in the trench. The method includes removing the second mask layer covering the bottom surface to form a second trench in the second mask layer. The second trench exposes the bottom surface and is over a first portion of the dielectric layer. The remaining second mask layer covers the inner wall. The method includes removing the first portion, the first mask layer, and the second mask layer to form a third trench in the dielectric layer. The method includes forming a conductive structure in the third trench.

公开(公告)号：US09812569B2

公开(公告)日：2017-11-07

申请号：US14224961

申请日：2014-03-25

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： I-Chih Chen ,  Ying-Lang Wang ,  Chih-Mu Huang ,  Ying-Hao Chen ,  Wen-Chang Kuo ,  Jung-Chi Jeng

IPC分类号： H01L29/78 ,  H01L29/167 ,  H01L29/08 ,  H01L29/66 ,  H01L29/165

CPC分类号： H01L29/7848 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66628 ,  H01L29/66636

摘要： A semiconductor device and a method of fabricating the semiconductor device are provided. The semiconductor device includes a substrate; a source/drain region having a first dopant in the substrate; a barrier layer having a second dopant formed around the source/drain region in the substrate. When a semiconductor device is scaled down, the doped profile in source/drain regions might affect the threshold voltage uniformity, the provided semiconductor device may improve the threshold voltage uniformity by the barrier layer to control the doped profile.

公开(公告)号：US11855175B2

公开(公告)日：2023-12-26

申请号：US17813652

申请日：2022-07-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Sung-Hsin Yang ,  Jung-Chi Jeng ,  Ru-Shang Hsiao

IPC分类号： H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/3213 ,  H01L21/8238 ,  H01L29/78

CPC分类号： H01L29/66484 ,  H01L21/32139 ,  H01L21/82385 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823456 ,  H01L21/823821 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/7855

摘要： Semiconductor devices and methods of forming the same are provided. An example method includes providing a workpiece including a first dummy gate stack and a second dummy gate stack in a first area of the workpiece, a third dummy gate stack and a fourth dummy gate stack in a second area of the workpiece, a hard mask layer over each of the first dummy gate stack, the second dummy gate stack, the third dummy gate stack, and the fourth dummy gate stack. The method further includes depositing a photoresist (PR) layer over the workpiece to form a first PR layer portion over the first area and a second PR layer portion over the second area; and selectively forming a first opening through the second PR layer portion over the third dummy gate stack and a second opening through the second PR layer portion over the fourth dummy gate stack.

公开(公告)号：US20230352483A1

公开(公告)日：2023-11-02

申请号：US18349486

申请日：2023-07-10

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Sung-Hsin Yang ,  Jung-Chi Jeng ,  Ru-Shang Hsiao

IPC分类号： H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/417

CPC分类号： H01L27/0886 ,  H01L29/6681 ,  H01L21/823468 ,  H01L29/785 ,  H01L21/823431 ,  H01L29/41791

摘要： Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a first transistor in a first area and a second transistor in a second area. The first transistor includes a first gate structure extending lengthwise along a first direction, and a first gate spacer, a second gate spacer, and a third gate spacer over sidewalls of the first gate structure. The second transistor includes a second gate structure extending lengthwise along the first direction, and the first gate spacer and the third gate spacer over sidewalls of the second gate structure. The first gate spacer, the second gate spacer and the third gate spacer are of different compositions and the third gate spacer is directly on the first gate spacer in the second area.

公开(公告)号：US20220376045A1

公开(公告)日：2022-11-24

申请号：US17882817

申请日：2022-08-08

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Sung-Hsin Yang ,  Jung-Chi Jeng ,  Ru-Shang Hsiao

IPC分类号： H01L29/06 ,  H01L29/66 ,  H03M1/06 ,  H01L21/027 ,  H01L21/311

摘要： Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a substrate having a first area and a second area, a plurality of fin structures extending along a direction over the first area and the second area of the substrate, a first transistor and a second transistor in the first area, a first isolation structure disposed between the first transistor and the second transistor, a first isolation structure disposed between the first transistor and the second transistor, a third transistor and a fourth transistor in the second area, and a second isolation structure disposed between the third transistor and the fourth transistor. The first isolation structure includes a first width along the direction and the second isolation structure includes a second width along the direction. The second width is greater than the first width.

公开(公告)号：US20220238521A1

公开(公告)日：2022-07-28

申请号：US17230117

申请日：2021-04-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Sung-Hsin Yang ,  Jung-Chi Jeng ,  Ru-Shang Hsiao

IPC分类号： H01L27/092 ,  H01L29/78 ,  H01L21/8234

摘要： In an embodiment, a device includes: an isolation region on a substrate; a fin structure protruding from between adjacent portions of the isolation region, the fin structure including a plurality of fins and a mesa, a channel region of the fin structure having a first portion in the fins and having a second portion in the mesa, the fins and the mesa being a continuous semiconductor material, the mesa having a greater width than the fins; and a first gate structure on the fin structure, the first gate structure extending along the first portion of the channel region in the fins and extending along the second portion of the channel region in the mesa.

公开(公告)号：US20150200299A1

公开(公告)日：2015-07-16

申请号：US14224961

申请日：2014-03-25

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： I-Chih CHEN ,  Ying-Lang Wang ,  Chih-Mu Huang ,  Ying-Hao Chen ,  Wen-Chang Kuo ,  Jung-Chi Jeng

IPC分类号： H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L29/161 ,  H01L29/167

CPC分类号： H01L29/7848 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66628 ,  H01L29/66636

摘要： A semiconductor device and a method of fabricating the semiconductor device are provided. The semiconductor device includes a substrate; a source/drain region having a first dopant in the substrate; a barrier layer having a second dopant formed around the source/drain region in the substrate. When a semiconductor device is scaled down, the doped profile in source/drain regions might affect the threshold voltage uniformity, the provided semiconductor device may improve the threshold voltage uniformity by the barrier layer to control the doped profile.

摘要翻译： 提供半导体器件和制造半导体器件的方法。 半导体器件包括衬底; 在衬底中具有第一掺杂剂的源/漏区; 阻挡层，其具有形成在衬底中的源极/漏极区周围的第二掺杂物。 当半导体器件按比例缩小时，源极/漏极区域中的掺杂分布可能影响阈值电压均匀性，所提供的半导体器件可以通过阻挡层来改善阈值电压均匀性以控制掺杂分布。

公开(公告)号：US11699702B2

公开(公告)日：2023-07-11

申请号：US17025802

申请日：2020-09-18

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Sung-Hsin Yang ,  Jung-Chi Jeng ,  Ru-Shang Hsiao

IPC分类号： H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/417

CPC分类号： H01L27/0886 ,  H01L21/823431 ,  H01L21/823468 ,  H01L29/41791 ,  H01L29/6681 ,  H01L29/785

摘要： Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a first transistor in a first area and a second transistor in a second area. The first transistor includes a first gate structure extending lengthwise along a first direction, and a first gate spacer, a second gate spacer, and a third gate spacer over sidewalls of the first gate structure. The second transistor includes a second gate structure extending lengthwise along the first direction, and the first gate spacer and the third gate spacer over sidewalls of the second gate structure. The first gate spacer, the second gate spacer and the third gate spacer are of different compositions and the third gate spacer is directly on the first gate spacer in the second area.

公开(公告)号：US11600727B2

公开(公告)日：2023-03-07

申请号：US16892458

申请日：2020-06-04

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Jung-Chi Jeng ,  I-Chih Chen ,  Wen-Chang Kuo ,  Ying-Hao Chen ,  Ru-Shang Hsiao ,  Chih-Mu Huang

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/66

摘要： A method for forming a semiconductor device is provided. The method includes forming an isolation structure in a semiconductor substrate. The method includes forming a gate over the semiconductor substrate. The method includes forming a support film over the isolation structure. The support film is a continuous film which continuously covers the isolation structure and the gate over the isolation structure, the support film conformally covers a first portion of a top surface and a second portion of a first sidewall of the gate, the top surface faces away from the semiconductor substrate, the support film and a topmost surface of the active region do not overlap with each other, and the topmost surface faces the gate. The method includes after forming the support film, forming lightly doped regions in the semiconductor substrate and at two opposite sides of the gate.