公开(公告)号：US20240387655A1

公开(公告)日：2024-11-21

申请号：US18787182

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Wei Chang ,  Hong-Ming Wu ,  Chen-Yuan Kao ,  Li-Hsiang Chao ,  Yi-Ying Liu

IPC: H01L29/417 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/538 ,  H01L29/40

Abstract: A method according to the present disclosure includes receiving a workpiece including a gate structure, a first source/drain (S/D) feature, a second S/D feature, a first dielectric layer over the gate structure, the first S/D feature, the second S/D feature, a first S/D contact over the first S/D feature, a second S/D contact over the second S/D feature, a first etch stop layer (ESL) over the first dielectric layer, and a second dielectric layer over the first ESL, forming a S/D contact via through the second dielectric layer and the first ESL to couple to the first S/D contact, forming a gate contact opening through the second dielectric layer, the first ESL, and the first dielectric layer to expose the gate structure, and forming a common rail opening adjoining the gate contact opening to expose the second S/D contact, and forming a common rail contact in the common rail opening.

公开(公告)号：US20200343087A1

公开(公告)日：2020-10-29

申请号：US16927638

申请日：2020-07-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Ting Lin ,  Chen-Yuan Kao ,  Rueijer Lin ,  Yu-Sheng Wang ,  I-Li Chen ,  Hong-Ming Wu

IPC: H01L21/02 ,  H01L29/51 ,  H01L21/768 ,  H01L21/285 ,  H01L29/417

Abstract: The present disclosure describes a method that includes forming a dielectric layer over a contact region on a substrate; etching the dielectric layer to form a contact opening to expose the contact region; and pre-cleaning the exposed contact region to remove a residual material formed by the etching. During the pre-cleaning, the contact region is exposed to an inductively coupled radio frequency (RF) plasma. Also, during the pre-cleaning, a direct current power supply unit (DC PSU) provides a bias voltage to the substrate and a magnetic field is applied to the inductively coupled RF plasma to collimate ions.

公开(公告)号：US11652149B2

公开(公告)日：2023-05-16

申请号：US17112782

申请日：2020-12-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Wei Chang ,  Hong-Ming Wu ,  Chen-Yuan Kao ,  Li-Hsiang Chao ,  Yi-Ying Liu

IPC: H01L29/417 ,  H01L29/40 ,  H01L23/538 ,  H01L23/522 ,  H01L21/768 ,  H01L21/8234

CPC classification number: H01L29/41775 ,  H01L21/76859 ,  H01L21/76877 ,  H01L21/823475 ,  H01L23/5221 ,  H01L23/5226 ,  H01L23/5386 ,  H01L29/401

Abstract: A method according to the present disclosure includes receiving a workpiece including a gate structure, a first source/drain (S/D) feature, a second S/D feature, a first dielectric layer over the gate structure, the first S/D feature, the second S/D feature, a first S/D contact over the first S/D feature, a second S/D contact over the second S/D feature, a first etch stop layer (ESL) over the first dielectric layer, and a second dielectric layer over the first ESL, forming a S/D contact via through the second dielectric layer and the first ESL to couple to the first S/D contact, forming a gate contact opening through the second dielectric layer, the first ESL, and the first dielectric layer to expose the gate structure, and forming a common rail opening adjoining the gate contact opening to expose the second S/D contact, and forming a common rail contact in the common rail opening.

公开(公告)号：US20230290842A1

公开(公告)日：2023-09-14

申请号：US18317538

申请日：2023-05-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Wei Chang ,  Hong-Ming Wu ,  Chen-Yuan Kao ,  Li-Hsiang Chao ,  Yi-Ying Liu

IPC: H01L29/417 ,  H01L23/522 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/40 ,  H01L23/538

CPC classification number: H01L29/41775 ,  H01L23/5221 ,  H01L21/76859 ,  H01L21/823475 ,  H01L23/5226 ,  H01L21/76877 ,  H01L29/401 ,  H01L23/5386

Abstract: A method according to the present disclosure includes receiving a workpiece including a gate structure, a first source/drain (S/D) feature, a second S/D feature, a first dielectric layer over the gate structure, the first S/D feature, the second S/D feature, a first S/D contact over the first S/D feature, a second S/D contact over the second S/D feature, a first etch stop layer (ESL) over the first dielectric layer, and a second dielectric layer over the first ESL, forming a S/D contact via through the second dielectric layer and the first ESL to couple to the first S/D contact, forming a gate contact opening through the second dielectric layer, the first ESL, and the first dielectric layer to expose the gate structure, and forming a common rail opening adjoining the gate contact opening to expose the second S/D contact, and forming a common rail contact in the common rail opening.

公开(公告)号：US10714329B2

公开(公告)日：2020-07-14

申请号：US16146529

申请日：2018-09-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Ting Lin ,  Chen-Yuan Kao ,  Rueijer Lin ,  Yu-Sheng Wang ,  I-Li Chen ,  Hong-Ming Wu

IPC: H01L21/4763 ,  H01L21/02 ,  H01L29/51 ,  H01L21/768 ,  H01L21/285 ,  H01L29/417

Abstract: The present disclosure describes a method that includes forming a dielectric layer over a contact region on a substrate; etching the dielectric layer to form a contact opening to expose the contact region; and pre-cleaning the exposed contact region to remove a residual material formed by the etching. During the pre-cleaning, the first contact region is exposed to an inductively coupled radio frequency (RF) plasma. Also, during the pre-cleaning, a direct current power supply unit (DC PSU) provides a bias voltage to the substrate and a magnetic field is applied to the inductively coupled RF plasma to collimate ions.