公开(公告)号：US20230274983A1

公开(公告)日：2023-08-31

申请号：US18312647

申请日：2023-05-05

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ya-Wen Chiu ,  Da-Yuan Lee ,  Hsien-Ming Lee ,  Kai-Cyuan Yang ,  Yu-Sheng Wang ,  Chih-Hsiang Fan ,  Kun-Wa Kuok

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/823821 ,  H01L21/823814 ,  H01L21/823828 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/513

摘要： A method includes forming a first transistor, which includes forming a first gate dielectric layer over a first channel region in a substrate and forming a first work-function layer over the first gate dielectric layer, wherein forming the first work-function layer includes depositing a work-function material using first process conditions to form the work-function material having a first proportion of different crystalline orientations and forming a second transistor, which includes forming a second gate dielectric layer over a second channel region in the substrate and forming a second work-function layer over the second gate dielectric layer, wherein forming the second work-function layer includes depositing the work-function material using second process conditions to form the work-function material having a second proportion of different crystalline orientations.

公开(公告)号：US11024505B2

公开(公告)日：2021-06-01

申请号：US16203832

申请日：2018-11-29

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsiao-Kuan Wei ,  Hsien-Ming Lee ,  Chin-You Hsu ,  Hsin-Yun Hsu ,  Pin-Hsuan Yeh

IPC分类号： H01L21/28 ,  H01L29/51 ,  H01L21/285 ,  H01L29/40 ,  H01L29/49 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66

摘要： Generally, the present disclosure provides example embodiments relating to formation of a gate structure of a device, such as in a replacement gate process, and the device formed thereby. In an example method, a gate dielectric layer is formed over an active area on a substrate. A dummy layer that contains a passivating species (such as fluorine) is formed over the gate dielectric layer. A thermal process is performed to drive the passivating species from the dummy layer into the gate dielectric layer. The dummy layer is removed. A metal gate electrode is formed over the gate dielectric layer. The gate dielectric layer includes the passivating species before the metal gate electrode is formed.

公开(公告)号：US10854459B2

公开(公告)日：2020-12-01

申请号：US15824474

申请日：2017-11-28

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsiao-Kuan Wei ,  Hsien-Ming Lee ,  Chin-You Hsu ,  Hsin-Yun Hsu ,  Pin-Hsuan Yeh

IPC分类号： H01L21/28 ,  H01L29/51 ,  H01L21/285 ,  H01L29/40 ,  H01L29/49 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66

摘要： Generally, the present disclosure provides example embodiments relating to formation of a gate structure of a device, such as in a replacement gate process, and the device formed thereby. In an example method, a gate dielectric layer is formed over an active area on a substrate. A dummy layer that contains a passivating species (such as fluorine) is formed over the gate dielectric layer. A thermal process is performed to drive the passivating species from the dummy layer into the gate dielectric layer. The dummy layer is removed. A metal gate electrode is formed over the gate dielectric layer. The gate dielectric layer includes the passivating species before the metal gate electrode is formed.

公开(公告)号：US20200287014A1

公开(公告)日：2020-09-10

申请号：US16884053

申请日：2020-05-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jui-Fen Chien ,  Hsiao-Kuan Wei ,  Hsien-Ming Lee ,  Chin-You Hsu

IPC分类号： H01L29/49 ,  H01L29/06 ,  H01L29/78 ,  H01L27/092 ,  H01L29/66 ,  H01L21/28

摘要： Provided is a semiconductor device including a first n-type fin field effect transistor (FinFET) and a second n-type FinFET. The first FinFET includes a first work function layer. The first work function layer includes a first portion of a first layer. The second n-type FinFET includes a second work function layer. The second work function layer includes a second portion of the first layer and a first portion of a second layer underlying the second portion of the first layer. A thickness of the first work function layer is less than a thickness of the second work function layer. A method of manufacturing the semiconductor device is also provided.

公开(公告)号：US20190148510A1

公开(公告)日：2019-05-16

申请号：US15877391

申请日：2018-01-23

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jui-Fen Chien ,  Hsiao-Kuan Wei ,  Hsien-Ming Lee ,  Chin-You Hsu

IPC分类号： H01L29/49 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L27/092

摘要： Provided is a semiconductor device including a fin-type field effect transistor (FinFET). The first FinFET includes a first gate structure and the first gate structure includes a first work function layer. The first work function layer includes a first layer and a second layer. The first layer is disposed over the second layer. The second layer includes a base material and a dopant doped in the base material. The dopant comprises Al, Ta, W, or a combination thereof. The first layer and the second layer comprise different materials. A method of manufacturing the semiconductor device is also provided.

公开(公告)号：US20240363627A1

公开(公告)日：2024-10-31

申请号：US18767022

申请日：2024-07-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuan-Chang Chiu ,  Chia-Ching Lee ,  Chien-Hao Chen ,  Hung-Chin Chung ,  Hsien-Ming Lee ,  Chi On Chui ,  Hsuan-Yu Tung ,  Chung-Chiang Wu

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L27/0886 ,  H01L21/823431 ,  H01L29/41791 ,  H01L29/42372 ,  H01L29/6681 ,  H01L29/785

摘要： A structure includes a semiconductor substrate including a first semiconductor region and a second semiconductor region, a first transistor in the first semiconductor region, and a second transistor in the second semiconductor region. The first transistor includes a first gate dielectric over the first semiconductor region, a first work function layer over and contacting the first gate dielectric, and a first conductive region over the first work function layer. The second transistor includes a second gate dielectric over the second semiconductor region, a second work function layer over and contacting the second gate dielectric, wherein the first work function layer and the second work function layer have different work functions, and a second conductive region over the second work function layer.

公开(公告)号：US12100751B2

公开(公告)日：2024-09-24

申请号：US18123596

申请日：2023-03-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Hsiang Fan ,  Tsung-Han Shen ,  Jia-Ming Lin ,  Wei-Chin Lee ,  Hsien-Ming Lee ,  Chi On Chui

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/78

CPC分类号： H01L29/6681 ,  H01L21/02274 ,  H01L21/823431 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7851

摘要： A method of forming a semiconductor device includes: forming a dummy gate over a fin, where the fin protrudes above a substrate; surrounding the dummy gate with a dielectric material; and replacing the dummy gate with a replacement gate structure, where replacing the dummy gate includes: forming a gate trench in the dielectric material, where forming the gate trench includes removing the dummy gate; forming a metal-gate stack in the gate trench, where forming the metal-gate stack includes forming a gate dielectric layer, a first work function layer, and a gap-filling material sequentially in the gate trench; and enlarging a volume of the gap-filling material in the gate trench.

公开(公告)号：US11735481B2

公开(公告)日：2023-08-22

申请号：US17391220

申请日：2021-08-02

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shao-Jyun Wu ,  Hung-Chi Wu ,  Chia-Ching Lee ,  Pin-Hsuan Yeh ,  Hung-Chin Chung ,  Hsien-Ming Lee ,  Chien-Hao Chen ,  Sheng-Liang Pan ,  Huan-Just Lin

IPC分类号： H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/02

CPC分类号： H01L21/823431 ,  H01L21/0234 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

摘要： An improved work function layer and a method of forming the same are disclosed. In an embodiment, the method includes forming a semiconductor fin extending from a substrate; depositing a dielectric layer over the semiconductor fin; depositing a first work function layer over the dielectric layer; and exposing the first work function layer to a metastable plasma of a first reaction gas, a metastable plasma of a generation gas, and a metastable plasma of a second reaction gas, the first reaction gas being different from the second reaction gas.

公开(公告)号：US20220359296A1

公开(公告)日：2022-11-10

申请号：US17870343

申请日：2022-07-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chia-Ching Lee ,  Hsin-Han Tsai ,  Shih-Hang Chiu ,  Tsung-Ta Tang ,  Chung-Chiang Wu ,  Hung-Chin Chung ,  Hsien-Ming Lee ,  Da-Yuan Lee ,  Jian-Hao Chen ,  Chien-Hao Chen ,  Kuo-Feng Yu ,  Chia-Wei Chen ,  Chih-Yu Hsu

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L29/40 ,  H01L29/66

摘要： A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.

公开(公告)号：US20210083118A1

公开(公告)日：2021-03-18

申请号：US16571879

申请日：2019-09-16

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chung-Chiang Wu ,  Po-Cheng Chen ,  Kuo-Chan Huang ,  Hung-Chin Chung ,  Hsien-Ming Lee ,  Chien-Hao Chen

IPC分类号： H01L29/78 ,  H01L27/088 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/40 ,  H01L21/8234

摘要： A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.