公开(公告)号：US20220328683A1

公开(公告)日：2022-10-13

申请号：US17852755

申请日：2022-06-29

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chun-Neng Lin ,  Ming-Hsi Yeh ,  Hung-Chin Chung ,  Hsin-Yun Hsu

IPC分类号： H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092

摘要： A semiconductor device includes a first fin, a second fin, and a third fin protruding above a substrate, where the third fin is between the first fin and the second fin; a gate dielectric layer over the first fin, the second fin, and the third fin; a first work function layer over and contacting the gate dielectric layer, where the first work function layer extends along first sidewalls and a first upper surface of the first fin; a second work function layer over and contacting the gate dielectric layer, where the second work function layer extends along second sidewalls and a second upper surface of the second fin, where the first work function layer and the second work function layer comprise different materials; and a first gate electrode over the first fin, a second gate electrode over the second fin, and a third gate electrode over the third fin.

公开(公告)号：US20220328309A1

公开(公告)日：2022-10-13

申请号：US17853600

申请日：2022-06-29

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Chien Chi ,  Pei-Hsuan Lee ,  Hung-Wen Su ,  Hsiao-Kuan Wei ,  Jui-Fen Chien ,  Hsin-Yun Hsu

IPC分类号： H01L21/02 ,  H01L21/20 ,  H01L29/66 ,  H01L21/762 ,  H01L29/49 ,  H01L21/324 ,  H01L21/28 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78 ,  H01L21/3205 ,  H01L29/417 ,  H01L21/3105 ,  H01L21/768

摘要： Embodiments disclosed herein relate generally to capping processes and structures formed thereby. In an embodiment, a conductive feature, formed in a dielectric layer, has a metallic surface, and the dielectric layer has a dielectric surface. The dielectric surface is modified to be hydrophobic by performing a surface modification treatment. After modifying the dielectric surface, a capping layer is formed on the metallic surface by performing a selective deposition process. In another embodiment, a surface of a gate structure is exposed through a dielectric layer. A capping layer is formed on the surface of the gate structure by performing a selective deposition process.

公开(公告)号：US11201227B2

公开(公告)日：2021-12-14

申请号：US15964769

申请日：2018-04-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsin-Yun Hsu ,  Hsiao-Kuan Wei

IPC分类号： H01L29/49 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417

摘要： A semiconductor device structure is provided. The semiconductor device structure includes a first insulating layer over a substrate. A first metal layer is formed in the first insulating layer and over the substrate. A silicon- and fluorine-containing barrier layer is formed between the first insulating layer and the first metal layer and between the substrate and the first metal layer. The silicon- and fluorine-containing barrier layer has a silicon content in a range from about 5% to about 20%.

公开(公告)号：US10790142B2

公开(公告)日：2020-09-29

申请号：US15880389

申请日：2018-01-25

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Chien Chi ,  Hsiao-Kuan Wei ,  Hung-Wen Su ,  Pei-Hsuan Lee ,  Hsin-Yun Hsu ,  Jui-Fen Chien

IPC分类号： H01L21/02 ,  H01L21/20 ,  H01L29/66 ,  H01L21/762 ,  H01L29/49 ,  H01L29/423 ,  H01L21/28 ,  H01L27/092 ,  H01L21/324 ,  H01L29/78 ,  H01L21/3205 ,  H01L29/417 ,  H01L21/3105 ,  H01L21/768

摘要： Embodiments disclosed herein relate generally to capping processes and structures formed thereby. In an embodiment, a conductive feature, formed in a dielectric layer, has a metallic surface, and the dielectric layer has a dielectric surface. The dielectric surface is modified to be hydrophobic by performing a surface modification treatment. After modifying the dielectric surface, a capping layer is formed on the metallic surface by performing a selective deposition process. In another embodiment, a surface of a gate structure is exposed through a dielectric layer. A capping layer is formed on the surface of the gate structure by performing a selective deposition process.

公开(公告)号：US20230317457A1

公开(公告)日：2023-10-05

申请号：US18330885

申请日：2023-06-07

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsiao-Kuan Wei ,  Hsien-Ming Lee ,  Chin-You Hsu ,  Hsin-Yun Hsu ,  Pin-Hsuan Yeh

IPC分类号： H01L21/28 ,  H01L29/51 ,  H01L21/285 ,  H01L29/40 ,  H01L29/49 ,  H01L21/3213 ,  H01L21/02

CPC分类号： H01L21/28185 ,  H01L29/513 ,  H01L21/28556 ,  H01L29/401 ,  H01L29/4966 ,  H01L21/32134 ,  H01L21/02321 ,  H01L21/28097 ,  H01L21/28518 ,  H01L21/28568 ,  H01L29/785

摘要： Generally, the present disclosure provides example embodiments relating to formation of a gate structure of a device, such as in a replacement gate process, and the device formed thereby. In an example method, a gate dielectric layer is formed over an active area on a substrate. A dummy layer that contains a passivating species (such as fluorine) is formed over the gate dielectric layer. A thermal process is performed to drive the passivating species from the dummy layer into the gate dielectric layer. The dummy layer is removed. A metal gate electrode is formed over the gate dielectric layer. The gate dielectric layer includes the passivating species before the metal gate electrode is formed.

公开(公告)号：US11710638B2

公开(公告)日：2023-07-25

申请号：US17334255

申请日：2021-05-28

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsiao-Kuan Wei ,  Hsien-Ming Lee ,  Chin-You Hsu ,  Hsin-Yun Hsu ,  Pin-Hsuan Yeh

IPC分类号： H01L21/28 ,  H01L29/51 ,  H01L21/285 ,  H01L29/40 ,  H01L29/49 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L21/28185 ,  H01L21/02321 ,  H01L21/28556 ,  H01L21/32134 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/513 ,  H01L21/28088 ,  H01L21/28097 ,  H01L21/28518 ,  H01L21/28568 ,  H01L29/66795 ,  H01L29/785

摘要： Generally, the present disclosure provides example embodiments relating to formation of a gate structure of a device, such as in a replacement gate process, and the device formed thereby. In an example method, a gate dielectric layer is formed over an active area on a substrate. A dummy layer that contains a passivating species (such as fluorine) is formed over the gate dielectric layer. A thermal process is performed to drive the passivating species from the dummy layer into the gate dielectric layer. The dummy layer is removed. A metal gate electrode is formed over the gate dielectric layer. The gate dielectric layer includes the passivating species before the metal gate electrode is formed.

公开(公告)号：US20240313114A1

公开(公告)日：2024-09-19

申请号：US18673615

申请日：2024-05-24

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chun-Neng Lin ,  Ming-Hsi Yeh ,  Hung-Chin Chung ,  Hsin-Yun Hsu

IPC分类号： H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66

CPC分类号： H01L29/785 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/66545 ,  H01L29/66795

摘要： A semiconductor device includes a first fin, a second fin, and a third fin protruding above a substrate, where the third fin is between the first fin and the second fin; a gate dielectric layer over the first fin, the second fin, and the third fin; a first work function layer over and contacting the gate dielectric layer, where the first work function layer extends along first sidewalls and a first upper surface of the first fin; a second work function layer over and contacting the gate dielectric layer, where the second work function layer extends along second sidewalls and a second upper surface of the second fin, where the first work function layer and the second work function layer comprise different materials; and a first gate electrode over the first fin, a second gate electrode over the second fin, and a third gate electrode over the third fin.

公开(公告)号：US12051753B2

公开(公告)日：2024-07-30

申请号：US17852755

申请日：2022-06-29

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chun-Neng Lin ,  Ming-Hsi Yeh ,  Hung-Chin Chung ,  Hsin-Yun Hsu

IPC分类号： H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66

CPC分类号： H01L29/785 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/66545 ,  H01L29/66795

摘要： A semiconductor device includes a first fin, a second fin, and a third fin protruding above a substrate, where the third fin is between the first fin and the second fin; a gate dielectric layer over the first fin, the second fin, and the third fin; a first work function layer over and contacting the gate dielectric layer, where the first work function layer extends along first sidewalls and a first upper surface of the first fin; a second work function layer over and contacting the gate dielectric layer, where the second work function layer extends along second sidewalls and a second upper surface of the second fin, where the first work function layer and the second work function layer comprise different materials; and a first gate electrode over the first fin, a second gate electrode over the second fin, and a third gate electrode over the third fin.

公开(公告)号：US11830742B2

公开(公告)日：2023-11-28

申请号：US17853600

申请日：2022-06-29

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Chien Chi ,  Pei-Hsuan Lee ,  Hung-Wen Su ,  Hsiao-Kuan Wei ,  Jui-Fen Chien ,  Hsin-Yun Hsu

IPC分类号： H01L21/02 ,  H01L21/20 ,  H01L29/66 ,  H01L21/762 ,  H01L29/49 ,  H01L21/324 ,  H01L21/28 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78 ,  H01L21/3205 ,  H01L29/417 ,  H01L21/3105 ,  H01L21/768

CPC分类号： H01L21/3105 ,  H01L21/02362 ,  H01L21/02639 ,  H01L21/28088 ,  H01L21/28194 ,  H01L21/3245 ,  H01L21/32051 ,  H01L21/768 ,  H01L21/76262 ,  H01L27/0924 ,  H01L29/41791 ,  H01L29/4238 ,  H01L29/4975 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/76224

摘要： Embodiments disclosed herein relate generally to capping processes and structures formed thereby. In an embodiment, a conductive feature, formed in a dielectric layer, has a metallic surface, and the dielectric layer has a dielectric surface. The dielectric surface is modified to be hydrophobic by performing a surface modification treatment. After modifying the dielectric surface, a capping layer is formed on the metallic surface by performing a selective deposition process. In another embodiment, a surface of a gate structure is exposed through a dielectric layer. A capping layer is formed on the surface of the gate structure by performing a selective deposition process.

公开(公告)号：US11145747B2

公开(公告)日：2021-10-12

申请号：US15901992

申请日：2018-02-22

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsin-Yun Hsu ,  Hsiao-Kuan Wei

IPC分类号： H01L29/66 ,  H01L21/321 ,  H01L21/28 ,  H01L29/78 ,  H01L29/49 ,  H01L29/423

摘要： A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a fin structure protruding therefrom, an insulating layer is over the substrate to cover the fin structure, a gate structure in the insulating layer and over the fin structure, and source and drain features covered by the insulating layer and over the fin structure on opposing sidewall surfaces of the gate structure. The gate structure includes a gate electrode layer, a conductive sealing layer covering the gate electrode layer, and a gate dielectric layer between the fin structure and the gate electrode layer and surrounding the gate electrode layer and the conductive sealing layer. The gate electrode layer has a material removal rate that is higher than the material removal rate of the conductive sealing layer in a chemical mechanical polishing process.