公开(公告)号：US12148810B2

公开(公告)日：2024-11-19

申请号：US18154087

申请日：2023-01-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hang Chiu ,  Chung-Chiang Wu ,  Jo-Chun Hung ,  Wei-Cheng Wang ,  Kuan-Ting Liu ,  Chi On Chui

IPC: H01L29/49 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: Semiconductor devices having improved gate electrode structures and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a gate structure over a semiconductor substrate, the gate structure including a high-k dielectric layer; an n-type work function layer over the high-k dielectric layer; an anti-reaction layer over the n-type work function layer, the anti-reaction layer including a dielectric material; a p-type work function layer over the anti-reaction layer, the p-type work function layer covering top surfaces of the anti-reaction layer; and a conductive cap layer over the p-type work function layer.

公开(公告)号：US11270994B2

公开(公告)日：2022-03-08

申请号：US15957912

申请日：2018-04-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ji-Cheng Chen ,  Ching-Hwanq Su ,  Kuan-Ting Liu ,  Shih-Hang Chiu

IPC: H01L27/088 ,  H01L29/49 ,  H01L29/423 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/66 ,  H01L21/28 ,  H01L21/02 ,  H01L21/285 ,  H01L29/51 ,  H01L21/3105 ,  H01L29/78

Abstract: A gate structure includes a gate dielectric layer, a work function layer, a metal layer, and a barrier layer. The work function layer is on the gate dielectric layer. The metal layer is over the work function layer. The barrier layer is sandwiched between the metal layer and the work function layer. The barrier layer includes silicon or aluminum.

公开(公告)号：US11075275B2

公开(公告)日：2021-07-27

申请号：US15909815

申请日：2018-03-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hang Chiu ,  Chung-Chiang Wu ,  Ching-Hwanq Su ,  Da-Yuan Lee ,  Ji-Cheng Chen ,  Kuan-Ting Liu ,  Tai-Wei Hwang ,  Chung-Yi Su

IPC: H01L29/49 ,  H01L27/088 ,  H01L21/3213 ,  H01L21/28 ,  H01L21/285 ,  H01L29/51 ,  H01L21/8234

Abstract: Certain embodiments of a semiconductor device and a method of forming a semiconductor device comprise forming a high-k gate dielectric layer over a short channel semiconductor fin. A work function metal layer is formed over the high-k gate dielectric layer. A seamless metal fill layer is conformally formed over the work function metal layer.

公开(公告)号：US20200321252A1

公开(公告)日：2020-10-08

申请号：US16907570

申请日：2020-06-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Wu ,  Wei-Chin Lee ,  Shih-Hang Chiu ,  Chia-Ching Lee ,  Hsueh Wen Tsau ,  Cheng-Yen Tsai ,  Cheng-Lung Hung ,  Da-Yuan Lee ,  Ching-Hwanq Su

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/78

Abstract: Semiconductor device structures having gate structures with tunable threshold voltages are provided. Various geometries of device structure can be varied to tune the threshold voltages. In some examples, distances from tops of fins to tops of gate structures can be varied to tune threshold voltages. In some examples, distances from outermost sidewalls of gate structures to respective nearest sidewalls of nearest fins to the respective outermost sidewalls (which respective gate structure overlies the nearest fin) can be varied to tune threshold voltages.

公开(公告)号：US20240222108A1

公开(公告)日：2024-07-04

申请号：US18608560

申请日：2024-03-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ching Lee ,  Chung-Chiang Wu ,  Shih-Hang Chiu ,  Hsuan-Yu Tung ,  Da-Yuan Lee

IPC: H01L21/02 ,  H01L21/768 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L21/02175 ,  H01L21/76841 ,  H01L21/76871 ,  H01L27/0886 ,  H01L29/66871

Abstract: A method includes depositing a first work-function layer and a second work-function layer in a first device region and a second device region, respectively, and depositing a first fluorine-blocking layer and a second fluorine-blocking layer in the first device region and the second device region, respectively. The first fluorine-blocking layer is over the first work-function layer, and the second fluorine-blocking layer is over the second work-function layer. The method further includes removing the second fluorine-blocking layer, and forming a first metal-filling layer over the first fluorine-blocking layer, and a second metal-filling layer over the second work-function layer.

公开(公告)号：US20230155002A1

公开(公告)日：2023-05-18

申请号：US17700998

申请日：2022-03-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hang Chiu ,  Wei-Cheng Wang ,  Chung-Chiang Wu ,  Chi On Chui

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/0259 ,  H01L21/28088 ,  H01L29/0665 ,  H01L29/4908 ,  H01L29/42392 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78696

Abstract: Embodiments provide a replacement metal gate in a FinFET or nanoFET which utilizes a conductive metal fill. The conductive metal fill has an upper surface which has a fin shape which may be used for a self-aligned contact.

公开(公告)号：US20230140968A1

公开(公告)日：2023-05-11

申请号：US18154087

申请日：2023-01-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hang Chiu ,  Chung-Chiang Wu ,  Jo-Chun Hung ,  Wei-Cheng Wang ,  Kuan-Ting Liu ,  Chi On Chui

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/28

CPC classification number: H01L29/4908 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696 ,  H01L21/02603 ,  H01L29/66742 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/66553 ,  H01L29/66545 ,  H01L21/28088

Abstract: Semiconductor devices having improved gate electrode structures and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a gate structure over a semiconductor substrate, the gate structure including a high-k dielectric layer; an n-type work function layer over the high-k dielectric layer; an anti-reaction layer over the n-type work function layer, the anti-reaction layer including a dielectric material; a p-type work function layer over the anti-reaction layer, the p-type work function layer covering top surfaces of the anti-reaction layer; and a conductive cap layer over the p-type work function layer.

公开(公告)号：US20220359296A1

公开(公告)日：2022-11-10

申请号：US17870343

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ching Lee ,  Hsin-Han Tsai ,  Shih-Hang Chiu ,  Tsung-Ta Tang ,  Chung-Chiang Wu ,  Hung-Chin Chung ,  Hsien-Ming Lee ,  Da-Yuan Lee ,  Jian-Hao Chen ,  Chien-Hao Chen ,  Kuo-Feng Yu ,  Chia-Wei Chen ,  Chih-Yu Hsu

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/40 ,  H01L29/66

Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.

公开(公告)号：US11289480B2

公开(公告)日：2022-03-29

申请号：US17000632

申请日：2020-08-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Wu ,  Shih-Hang Chiu ,  Chih-Chang Hung ,  I-Wei Yang ,  Shu-Yuan Ku ,  Cheng-Lung Hung ,  Da-Yuan Lee ,  Ching-Hwanq Su

IPC: H01L27/088 ,  H01L29/06 ,  H01L27/11 ,  H01L21/8234 ,  H01L29/66

Abstract: A method includes forming a first semiconductor fin in a substrate, forming a metal gate structure over the first semiconductor fin, removing a portion of the metal gate structure to form a first recess in the metal gate structure that is laterally separated from the first semiconductor fin by a first distance, wherein the first distance is determined according to a first desired threshold voltage associated with the first semiconductor fin, and filling the recess with a dielectric material.

公开(公告)号：US20190326281A1

公开(公告)日：2019-10-24

申请号：US15957912

申请日：2018-04-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ji-Cheng Chen ,  Ching-Hwanq Su ,  Kuan-Ting Liu ,  Shih-Hang Chiu

IPC: H01L27/088 ,  H01L29/51 ,  H01L29/49 ,  H01L29/423 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/66 ,  H01L21/28 ,  H01L21/02 ,  H01L21/285

Abstract: A gate structure includes a gate dielectric layer, a work function layer, a metal layer, and a barrier layer. The work function layer is on the gate dielectric layer. The metal layer is over the work function layer. The barrier layer is sandwiched between the metal layer and the work function layer. The barrier layer includes silicon or aluminum.