公开(公告)号：US20240222108A1

公开(公告)日：2024-07-04

申请号：US18608560

申请日：2024-03-18

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chia-Ching Lee ,  Chung-Chiang Wu ,  Shih-Hang Chiu ,  Hsuan-Yu Tung ,  Da-Yuan Lee

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L27/088 ,  H01L29/66

CPC分类号： H01L21/02175 ,  H01L21/76841 ,  H01L21/76871 ,  H01L27/0886 ,  H01L29/66871

摘要： A method includes depositing a first work-function layer and a second work-function layer in a first device region and a second device region, respectively, and depositing a first fluorine-blocking layer and a second fluorine-blocking layer in the first device region and the second device region, respectively. The first fluorine-blocking layer is over the first work-function layer, and the second fluorine-blocking layer is over the second work-function layer. The method further includes removing the second fluorine-blocking layer, and forming a first metal-filling layer over the first fluorine-blocking layer, and a second metal-filling layer over the second work-function layer.

公开(公告)号：US20240021667A1

公开(公告)日：2024-01-18

申请号：US18152489

申请日：2023-01-10

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Cheng-Hao Hou ,  Shin-Hung Tsai ,  Da-Yuan Lee ,  Chi On Chui

IPC分类号： H01L23/522

CPC分类号： H01L28/92 ,  H01L23/5226 ,  H01L28/75 ,  H01L28/91

摘要： A method includes forming a first capacitor electrode; forming a first oxygen-blocking layer on the first capacitor electrode; forming an capacitor insulator layer on the first oxygen-blocking layer; forming a second oxygen-blocking layer on the capacitor insulator layer; forming a second capacitor electrode on the second oxygen-blocking layer; and forming a first contact plug that is electrically coupled to the first capacitor electrode and a second contact plug that is electrically coupled to the second capacitor electrode.

公开(公告)号：US20230163191A1

公开(公告)日：2023-05-25

申请号：US17713014

申请日：2022-04-04

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsin-Hua Lee ,  Da-Yuan Lee ,  Kuei-Lun Lin

IPC分类号： H01L29/51 ,  H01L29/40 ,  H01L21/02

CPC分类号： H01L29/517 ,  H01L29/511 ,  H01L29/401 ,  H01L21/02205 ,  H01L21/0228 ,  H01L29/0665

摘要： A semiconductor device is provided in accordance with some embodiments. The semiconductor device includes an interfacial layer disposed over a channel region, a gate dielectric structure disposed over the channel region, and a gate electrode disposed over the gate dielectric structure. The gate dielectric structure includes a first layer of an oxide of a first metal disposed over the interfacial layer and a second layer of an oxide or silicate of a second metal disposed over the first layer. The first layer has a first thickness, and the second layer has second a thickness that is at least three times greater than the first thickness. An oxygen areal density of the oxide of the first metal is greater than an oxygen areal density of the oxide of the second metal.

公开(公告)号：US20220359296A1

公开(公告)日：2022-11-10

申请号：US17870343

申请日：2022-07-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chia-Ching Lee ,  Hsin-Han Tsai ,  Shih-Hang Chiu ,  Tsung-Ta Tang ,  Chung-Chiang Wu ,  Hung-Chin Chung ,  Hsien-Ming Lee ,  Da-Yuan Lee ,  Jian-Hao Chen ,  Chien-Hao Chen ,  Kuo-Feng Yu ,  Chia-Wei Chen ,  Chih-Yu Hsu

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L29/40 ,  H01L29/66

摘要： A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.

公开(公告)号：US11302582B2

公开(公告)日：2022-04-12

申请号：US16686388

申请日：2019-11-18

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Cheng-Yen Tsai ,  Chung-Chiang Wu ,  Tai-Wei Hwang ,  Hung-Chin Chung ,  Wei-Chin Lee ,  Da-Yuan Lee ,  Ching-Hwanq Su ,  Yin-Chuan Chuang ,  Kuan-Ting Liu

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L21/02 ,  H01L29/51

摘要： Embodiments disclosed herein relate to a pre-deposition treatment of materials utilized in metal gates of different transistors on a semiconductor substrate. In an embodiment, a method includes exposing a first metal-containing layer of a first device and a second metal-containing layer of a second device to a reactant to form respective monolayers on the first and second metal-containing layers. The first and second devices are on a substrate. The first device includes a first gate structure including the first metal-containing layer. The second device includes a second gate structure including the second metal-containing layer different from the second metal-containing layer. The monolayers on the first and second metal-containing layers are exposed to an oxidant to provide a hydroxyl group (—OH) terminated surface for the monolayers. Thereafter, a third metal-containing layer is formed on the —OH terminated surfaces of the monolayers on the first and second metal-containing layers.

公开(公告)号：US11289480B2

公开(公告)日：2022-03-29

申请号：US17000632

申请日：2020-08-24

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chung-Chiang Wu ,  Shih-Hang Chiu ,  Chih-Chang Hung ,  I-Wei Yang ,  Shu-Yuan Ku ,  Cheng-Lung Hung ,  Da-Yuan Lee ,  Ching-Hwanq Su

IPC分类号： H01L27/088 ,  H01L29/06 ,  H01L27/11 ,  H01L21/8234 ,  H01L29/66

摘要： A method includes forming a first semiconductor fin in a substrate, forming a metal gate structure over the first semiconductor fin, removing a portion of the metal gate structure to form a first recess in the metal gate structure that is laterally separated from the first semiconductor fin by a first distance, wherein the first distance is determined according to a first desired threshold voltage associated with the first semiconductor fin, and filling the recess with a dielectric material.

公开(公告)号：US20210043521A1

公开(公告)日：2021-02-11

申请号：US17068041

申请日：2020-10-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ya-Wen Chiu ,  Da-Yuan Lee ,  Hsien-Ming Lee ,  Kai-Cyuan Yang ,  Yu-Sheng Wang ,  Chih-Hsiang Fan ,  Kun-Wa Kuok

IPC分类号： H01L21/8238 ,  H01L29/49 ,  H01L29/78 ,  H01L27/092 ,  H01L29/66 ,  H01L29/51

摘要： A method includes forming a first transistor, which includes forming a first gate dielectric layer over a first channel region in a substrate and forming a first work-function layer over the first gate dielectric layer, wherein forming the first work-function layer includes depositing a work-function material using first process conditions to form the work-function material having a first proportion of different crystalline orientations and forming a second transistor, which includes forming a second gate dielectric layer over a second channel region in the substrate and forming a second work-function layer over the second gate dielectric layer, wherein forming the second work-function layer includes depositing the work-function material using second process conditions to form the work-function material having a second proportion of different crystalline orientations.

公开(公告)号：US20200091006A1

公开(公告)日：2020-03-19

申请号：US16686408

申请日：2019-11-18

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Cheng-Yen Tsai ,  Chung-Chiang Wu ,  Tai-Wei Hwang ,  Hung-Chin Chung ,  Wei-Chin Lee ,  Da-Yuan Lee ,  Ching-Hwanq Su ,  Yin-Chuan Chuang ,  Kuan-Ting Liu

IPC分类号： H01L21/8234 ,  H01L21/02 ,  H01L29/51 ,  H01L27/088

摘要： Embodiments disclosed herein relate to a pre-deposition treatment of materials utilized in metal gates of different transistors on a semiconductor substrate. In an embodiment, a method includes exposing a first metal-containing layer of a first device and a second metal-containing layer of a second device to a reactant to form respective monolayers on the first and second metal-containing layers. The first and second devices are on a substrate. The first device includes a first gate structure including the first metal-containing layer. The second device includes a second gate structure including the second metal-containing layer different from the second metal-containing layer. The monolayers on the first and second metal-containing layers are exposed to an oxidant to provide a hydroxyl group (—OH) terminated surface for the monolayers. Thereafter, a third metal-containing layer is formed on the —OH terminated surfaces of the monolayers on the first and second metal-containing layers.

公开(公告)号：US09837507B1

公开(公告)日：2017-12-05

申请号：US15281305

申请日：2016-09-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Yu-Sheng Wang ,  Chi-Cheng Hung ,  Da-Yuan Lee ,  Hsin-Yi Lee ,  Kuan-Ting Liu

IPC分类号： H01L29/66 ,  H01L29/49

CPC分类号： H01L29/66545 ,  H01L29/4966 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

摘要： A field effect transistor includes a channel layer made of a semiconductor and a metal gate structure. The metal gate structure includes a gate dielectric layer, a barrier layer formed on the gate dielectric layer, a work function adjustment layer formed on the barrier layer and made of one of Al and TiAl, a blocking layer formed on the work function adjustment layer and made of TiN, and a body metal layer formed on the blocking layer and made of W. A gate length over the channel layer is in a range from 5 nm to 15 nm, and a thickness of the first conductive layer is in a range of 0.2 nm to 3.0 nm. A range between a largest thickness and a smallest thickness of the first conductive layer is more than 0% and less than 10% of an average thickness of the first conductive layer.

公开(公告)号：US09761683B2

公开(公告)日：2017-09-12

申请号：US14714221

申请日：2015-05-15

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Chun-Yuan Chou ,  Chung-Chiang Wu ,  Da-Yuan Lee ,  Weng Chang

IPC分类号： H01L29/78 ,  H01L29/49 ,  H01L29/66 ,  H01L21/28 ,  H01L29/06 ,  H01L21/285 ,  H01L21/768

CPC分类号： H01L29/495 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28562 ,  H01L21/76877 ,  H01L21/76879 ,  H01L29/0649 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

摘要： A method of manufacturing a Fin FET includes forming a fin structure including an upper layer. Part of the upper layer is exposed from an isolation insulating layer. A dummy gate structure is formed over part of the fin structure. The dummy gate structure includes a dummy gate electrode layer and a dummy gate dielectric layer. An interlayer insulating layer is formed over the dummy gate structure. The dummy gate structure is removed so that a space is formed. A gate dielectric layer is formed in the space. A first metal layer is formed over the gate dielectric in the space. A second metal layer is formed over the first metal layer in the space. The first and second metal layers are partially removed, thereby reducing a height of the first and second metal layers. A third metal layer is formed over the partially removed first and second metal layers.