Invention Grant
- Patent Title: Method of simultaneous silicidation on source and drain of NMOS and PMOS transistors
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Application No.: US17085850Application Date: 2020-10-30
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Publication No.: US12062579B2Publication Date: 2024-08-13
- Inventor: Xuebin Li
- Applicant: Applied Materials, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Applied Materials, Inc.
- Current Assignee: Applied Materials, Inc.
- Current Assignee Address: US CA Santa Clara
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; C23C16/42 ; C23C16/50 ; C23C16/52 ; H01J37/32 ; H01L21/285
Abstract:
A method and apparatus for the formation of a metal-oxide semiconductor FET (MOSFET) device is disclosed herein. The method of formation includes the utilization of a silicon-germanium seed layer deposited over an n-channel metal-oxide semiconductor (NMOS) device and a p-channel metal-oxide semiconductor (PMOS) device. The seed layer may be one seed layer deposited over both the NMOS source/drain regions and the PMOS source/drain regions or two doped seed layers wherein a first doped seed layer is deposited over the PMOS source/drain regions and a second doped seed layer is deposited over the NMOS source/drain regions. The seed layer enables simultaneous formation of a silicide over both the PMOS source/drain regions and the NMOS source/drain regions. The silicide formation consumes the seed layer and forms a silicide layer which varies in composition depending upon the composition of the absorbed seed layer.
Public/Granted literature
- US20220139784A1 METHOD OF SIMULTANEOUS SILICIDATION ON SOURCE AND DRAIN OF NMOS AND PMOS TRANSISTORS Public/Granted day:2022-05-05
Information query
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