公开(公告)号：US20240355741A1

公开(公告)日：2024-10-24

申请号：US18760444

申请日：2024-07-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shuen-Shin LIANG ,  Chun-I TSAI ,  Chih-Wei CHANG ,  Chun-Hsien HUANG ,  Hung-Yi HUANG ,  Keng-Chu LIN ,  Ken-Yu CHANG ,  Sung-Li WANG ,  Chia-Hung CHU ,  Hsu-Kai CHANG

IPC分类号： H01L23/532 ,  H01L21/285 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L23/53266 ,  H01L21/76802 ,  H01L21/7685 ,  H01L21/28568 ,  H01L21/76843 ,  H01L23/5226

摘要： The present disclosure describes a method for forming capping layers configured to prevent the migration of out-diffused cobalt atoms into upper metallization layers In some embodiments, the method includes depositing a cobalt diffusion barrier layer on a liner-free conductive structure that includes ruthenium, where depositing the cobalt diffusion barrier layer includes forming the cobalt diffusion barrier layer self-aligned to the liner-free conductive structure. The method also includes depositing, on the cobalt diffusion barrier layer, a stack with an etch stop layer and dielectric layer, and forming an opening in the stack to expose the cobalt diffusion barrier layer. Finally, the method includes forming a conductive structure on the cobalt diffusion barrier layer.

公开(公告)号：US20240038595A1

公开(公告)日：2024-02-01

申请号：US17876389

申请日：2022-07-28

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Kuan-Kan HU ,  Jhih-Rong HUANG ,  Yi-Bo LIAO ,  Shuen-Shin LIANG ,  Min-Chiang CHUANG ,  Sung-Li WANG ,  Wei-Yen WOON ,  Szuya LIAO

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/417 ,  H01L29/45 ,  H01L21/285

CPC分类号： H01L21/823871 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/45 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823821

摘要： A method for manufacturing a semiconductor device is provided. The method includes forming a first transistor over a substrate, wherein the first transistor comprises a first source/drain feature; depositing an interlayer dielectric layer around the first transistor; etching an opening in the interlayer dielectric layer to expose the first source/drain feature; conformably depositing a semimetal layer over the interlayer dielectric layer, wherein the semimetal layer has a first portion in the opening in the interlayer dielectric layer and a second portion over a top surface of the interlayer dielectric layer; and forming a source/drain contact in the opening in the interlayer dielectric layer.

公开(公告)号：US20240006505A1

公开(公告)日：2024-01-04

申请号：US17854676

申请日：2022-06-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Po-Chin CHANG ,  Yuting CHENG ,  Hsu-Kai CHANG ,  Chia-Hung CHU ,  Tzu-Pei CHEN ,  Shuen-Shin LIANG ,  Sung-Li WANG ,  Pinyen LIN ,  Lin-Yu HUANG

IPC分类号： H01L29/45 ,  H01L29/40

CPC分类号： H01L29/45 ,  H01L29/401

摘要： A semiconductor device includes a semiconductor structure, a conductive nitride feature, a third dielectric feature, and a conductive line feature. The semiconductor structure includes a substrate, two source/drain regions disposed in the substrate, a first dielectric feature disposed over the substrate, a gate structure disposed in the first dielectric feature and between the source/drain regions, a second dielectric feature disposed over the first dielectric feature, and a contact feature disposed in the second dielectric feature and being connected to at least one of the source/drain regions and the gate structure. The conductive nitride feature includes metal nitride or alloy nitride, is disposed in the second dielectric feature, and is connected to the contact feature. The third dielectric feature is disposed over the second dielectric feature. The conductive feature is disposed in the third dielectric feature and is connected to the conductive nitride feature opposite to the contact feature.

公开(公告)号：US20240312786A1

公开(公告)日：2024-09-19

申请号：US18671732

申请日：2024-05-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Sung-Li WANG ,  Yasutoshi OKUNO ,  Shih-Chuan CHIU

IPC分类号： H01L21/285 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/28518 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/76832 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823871 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/785

摘要： A method of forming a semiconductor device includes forming a source/drain region on a substrate, depositing a metal-rich metal silicide layer on the source/drain region, depositing a silicon-rich metal silicide layer on the metal-rich metal silicide layer, and forming a contact plug on the silicon-rich metal silicide layer. This disclosure also describes a semiconductor device including a fin structure on a substrate, a source/drain region on the fin structure, a metal-rich metal silicide layer on the source/drain region, a silicon-rich metal silicide layer on the metal-rich metal silicide layer, and a contact plug on the silicon-rich metal silicide layer.

公开(公告)号：US20230030411A1

公开(公告)日：2023-02-02

申请号：US17967499

申请日：2022-10-17

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chia-Hung CHU ,  Sung-Li WANG ,  Fang-Wei LEE ,  Jung-Hao CHANG ,  Mrunal Abhijith KHADERBAD ,  Keng-Chu LIN

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L21/311 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/45 ,  H01L29/08 ,  H01L21/762 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/308 ,  H01L21/027 ,  H01L21/3213

摘要： A fin field effect transistor device structure includes a fin structure formed over a substrate. The fin field effect transistor device structure also includes a source/drain epitaxial structure formed over the fin structure. The fin field effect transistor device structure also includes a contact structure with a concave top surface formed over the source/drain epitaxial structure. The fin field effect transistor device structure also includes a barrier layer conformally wrapped around the contact structure. The fin field effect transistor device structure also includes a via structure formed over the contact structure. The concave top surface of the contact structure is below the top surface of the barrier layer.

公开(公告)号：US20240055485A1

公开(公告)日：2024-02-15

申请号：US17886797

申请日：2022-08-12

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Cheng-Wei CHANG ,  Shahaji B. MORE ,  Shuen-Shin LIANG ,  Sung-Li WANG ,  Yi-Ying LIU

IPC分类号： H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/786 ,  H01L29/775 ,  H01L21/285 ,  H01L29/66

CPC分类号： H01L29/0847 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/78696 ,  H01L29/775 ,  H01L21/28518 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66439

摘要： A semiconductor device structure is provided. The semiconductor device structure includes a source/drain epitaxial feature disposed over a substrate, wherein the source/drain epitaxial feature comprises a first epitaxial layer, a second epitaxial layer in contact with the first epitaxial layer, wherein the second epitaxial layer has a first dopant concentration, and a third epitaxial layer having sidewalls enclosed by the second epitaxial layer, wherein the third epitaxial layer has a second dopant concentration higher than the first dopant concentration. The semiconductor device structure also includes a source/drain cap layer disposed above and in contact with the second epitaxial layer and the third epitaxial layer, wherein the source/drain cap layer has a third dopant concentration higher than the second dopant concentration, and a silicide layer disposed above and in contact with the source/drain cap layer.

公开(公告)号：US20230387316A1

公开(公告)日：2023-11-30

申请号：US17825516

申请日：2022-05-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shuen-Shin LIANG ,  Min-Chiang CHUANG ,  Chia-Cheng CHEN ,  Chun-Hung WU ,  Liang-Yin CHEN ,  Sung-Li WANG ,  Pinyen LIN ,  Kuan-Kan HU ,  Jhih-Rong HUANG ,  Szu-Hsian LEE ,  Tsun-Jen CHAN ,  Cheng-Wei LIAN ,  Po-Chin CHANG ,  Chuan-Hui SHEN ,  Lin-Yu HUANG ,  Yuting CHENG ,  Yan-Ming TSAI ,  Hong-Mao LEE

IPC分类号： H01L29/786 ,  H01L29/417

CPC分类号： H01L29/78651 ,  H01L29/41733

摘要： A semiconductor device includes a source/drain portion, a metal silicide layer disposed over the source/drain portion, and a transition layer disposed between the source/drain portion and the metal silicide layer. The transition layer includes implantation elements, and an atomic concentration of the implantation elements in the transition layer is higher than that in each of the source/drain portion and the metal silicide layer so as to reduce a contact resistance between the source/drain portion and the metal silicide layer. Methods for manufacturing the semiconductor device are also disclosed.

公开(公告)号：US20230230916A1

公开(公告)日：2023-07-20

申请号：US17577800

申请日：2022-01-18

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shuen-Shin LIANG ,  Chia-Hung CHU ,  Po-Chin CHANG ,  Tzu-Pei CHEN ,  Ken-Yu CHANG ,  Hung-Yi HUANG ,  Harry CHIEN ,  Wei-Yip LOH ,  Chun-I TSAI ,  Hong-Mao LEE ,  Sung-Li WANG ,  Pinyen LIN

IPC分类号： H01L23/522 ,  H01L29/40 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L29/401 ,  H01L21/76877 ,  H01L21/76843

摘要： A method for manufacturing a semiconductor device includes: forming a lower metal contact in a trench of a first dielectric structure, the lower metal contact having a height less than a depth of the trench and being made of a first metal material; forming an upper metal contact to fill the trench and to be in contact with the lower metal contact, the upper metal contact being formed of a second metal material different from the first metal material and having a bottom surface with a dimension the same as a dimension of a top surface of the lower metal contact; forming a second dielectric structure on the first dielectric structure; and forming a via contact penetrating through the second dielectric structure to be electrically connected to the upper metal contact, the via contact being formed of a metal material the same as the second metal material.

公开(公告)号：US20240332393A1

公开(公告)日：2024-10-03

申请号：US18741963

申请日：2024-06-13

申请人： Taiwan Semiconductor Manufacturing Company, LTD.

发明人： Hsu-Kai CHANG ,  Jhih-Rong HUANG ,  Yen-Tien TUNG ,  Chia-Hung CHU ,  Shuen-Shin LIANG ,  Tzer-Min SHEN ,  Pinyen LIN ,  Sung-Li WANG

IPC分类号： H01L29/45 ,  H01L21/285 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/45 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7851

摘要： A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second gate structures disposed on first and second fin structures, first and second source/drain (S/D) regions disposed on the first and second fin structures, first and second contact structures disposed on the first and second S/D regions, and a dipole layer disposed at an interface between the first nWFM silicide layer and the first S/D region. The first contact structure includes a first nWFM silicide layer disposed on the first S/D region and a first contact plug disposed on the first nWFM silicide layer. The second contact structure includes a pWFM silicide layer disposed on the second S/D region, a second nWFM silicide layer disposed on the pWFM silicide layer, and a second contact plug disposed on the pWFM silicide layer.

公开(公告)号：US20240313075A1

公开(公告)日：2024-09-19

申请号：US18182921

申请日：2023-03-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shuen-Shin LIANG ,  Kan-Ju LIN ,  Chia-Hung CHU ,  Chien CHANG ,  Harry CHIEN ,  Sung-Li WANG

IPC分类号： H01L29/423 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L29/42392 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

摘要： The present disclosure provides a method for semiconductor fabrication. The method includes depositing a first metal layer by a first deposition over a source/drain (S/D) feature and over side portions of a trench exposing the S/D feature. The first metal layer is thicker over the S/D feature than over side portions of the trench. The method includes growing a metal on the first metal layer by a second deposition to form a second metal layer filling up the trench. The second deposition is different from the first deposition and the growing of the metal in a vertical direction is grown at a faster rate than the growing of the metal in a horizontal direction. After growing the metal to form the second metal layer, the method includes planarizing the first and second metal layers to form an S/D contact. The method forms an S/D via on the second metal layer.