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公开(公告)号：US20230395429A1
公开(公告)日：2023-12-07
申请号：US17805605
申请日：2022-06-06
发明人： Kan-Ju LIN , Hao-Heng LIU , Chien CHANG , Hung-Yi HUANG , Harry CHIEN
IPC分类号： H01L21/768 , H01L23/522 , C23C16/56 , C23C16/14
CPC分类号： H01L21/76876 , H01L21/76873 , H01L21/76843 , H01L21/76865 , H01L23/5226 , C23C16/56 , C23C16/14 , H01L23/53223
摘要： Depositing a seed layer after formation of the MD in order to reduce or prevent epitaxial growth of the seed layer toward the MD. For example, the seed layer may be deposited using CVD and conformal dry etching. In some implementations, the seed layer may be formed of ruthenium (Ru), molybdenum (Mo), or tungsten (W). Accordingly, the seed layer helps reduce or prevent seam formation in the VG, which reduces resistance of the VG by allowing for bottom-up metal growth. Additionally, current leakage from the VG to the MD is reduced or even prevented. As a result, device performance and efficiency are increased and breakdown voltage of the gate structure is also increased. Additionally, because electrical shorts are less likely, yield is increased, which conserves power, raw materials, and processing resources that otherwise would have been consumed during manufacture.
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公开(公告)号：US20230054633A1
公开(公告)日：2023-02-23
申请号：US17445431
申请日：2021-08-19
发明人： Wei-Yip LOH , Yan-Ming TSAI , Yi-Ning TAI , Raghunath PUTIKAM , Hung-Yi HUANG , Hung-Hsu CHEN , Chih-Wei CHANG
IPC分类号： H01L21/8238 , H01L29/40
摘要： Techniques described herein enable respective (different) types of metal silicide layers to be formed for p-type source/drain regions and n-type source/drain regions in a selective manner. For example, a p-type metal silicide layer may be selectively formed over a p-type source/drain region (e.g., such that the p-type metal silicide layer is not formed over the n-type source/drain region) and an n-type metal silicide layer may be formed over the n-type source/drain region (which may be selective or non-selective). This provides a low Schottky barrier height between the p-type metal silicide layer and the p-type source/drain region, as well as a low Schottky barrier height between the n-type metal silicide layer and the n-type source/drain region. This reduces the contact resistance for both p-type source/drain regions and n-type source/drain regions.
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3.发明公开公开(公告)号：US20230402366A1
公开(公告)日：2023-12-14
申请号：US17836781
申请日：2022-06-09
发明人： Shuen-Shin LIANG , Chia-Hung CHU , Po-Chin CHANG , Hsu-Kai CHANG , Kuan-Kan HU , Ken-Yu CHANG , Hung-Yi HUANG , Harry CHIEN , Wei-Yip LOH , Chun-I TSAI , Hong-Mao LEE , Sung-Li WANG , Pinyen LIN , Chuan-Hui SHEN
IPC分类号： H01L23/522 , H01L23/532 , H01L21/768
CPC分类号： H01L23/5226 , H01L23/53266 , H01L21/76843 , H01L21/76883
摘要： A semiconductor device includes a substrate, a source/drain region disposed in the substrate, a silicide structure disposed on the source/drain region, a first dielectric layer disposed over the substrate, a conductive contact disposed in the first dielectric layer and over the silicide structure, a second dielectric layer disposed over the first dielectric layer, a via contact disposed in the second dielectric layer and connected to the conductive contact, and a first metal surrounding the via contact.
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公开(公告)号：US20230253308A1
公开(公告)日：2023-08-10
申请号：US17668482
申请日：2022-02-10
发明人： Chia-Hung CHU , Po-Chin CHANG , Tzu-Pei CHEN , Yuting CHENG , Kan-Ju LIN , Chih-Shiun CHOU , Hung-Yi HUANG , Pinyen LIN , Sung-Li WANG , Sheng-Tsung WANG , Lin-Yu HUANG , Shao-An WANG , Harry CHIEN
IPC分类号： H01L23/522 , H01L23/528 , H01L21/768
CPC分类号： H01L23/5226 , H01L23/5283 , H01L21/76816 , H01L21/76814 , H01L21/76843 , H01L21/76871 , H01L29/41775
摘要： A method for manufacturing a semiconductor device includes forming a conductive feature in a first dielectric layer; forming a second dielectric layer on the first dielectric layer; forming a trench that penetrates through the second dielectric layer, and terminates at the conductive feature; forming a contact layer in the trench and on the conductive feature; etching back the contact layer to form a first via contact feature in the trench, the first via contact feature being electrically connected to the conductive feature; and forming a second via contact feature on the first via contact feature in the trench.
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5.发明公开公开(公告)号：US20230299168A1
公开(公告)日：2023-09-21
申请号：US17695075
申请日：2022-03-15
发明人： Kuan-Kan HU , Shuen-Shin LIANG , Chia-Hung CHU , Po-Chin CHANG , Hsu-Kai CHANG , Ken-Yu CHANG , Wei-Yip LOH , Hung-Yi HUANG , Harry CHIEN , Sung-Li WANG , Pinyen LIN , Chuan-Hui SHEN , Tzu-Pei CHEN , Yuting CHENG
IPC分类号： H01L29/45 , H01L29/40 , H01L29/417
CPC分类号： H01L29/45 , H01L29/401 , H01L29/41791 , H01L29/41733 , H01L23/5226
摘要： A semiconductor device includes a semiconductor substrate, an epitaxial structure, a silicide structure, a conductive structure, and a protection segment. The epitaxial structure is disposed in the semiconductor substrate. The silicide structure is disposed in the epitaxial structure. The conductive structure is disposed over the silicide structure and is electrically connected to the silicide structure. The protection segment is made of metal nitride, is disposed over the silicide structure, and is disposed between the silicide structure and the conductive structure.
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公开(公告)号：US20230008239A1
公开(公告)日：2023-01-12
申请号：US17658901
申请日：2022-04-12
发明人： Chien CHANG , Min-Hsiu HUNG , Yu-Hsiang LIAO , Yu-Shiuan WANG , Tai Min CHANG , Kan-Ju LIN , Chih-Shiun CHOU , Hung-Yi HUANG , Chih-Wei CHANG , Ming-Hsing TSAI
IPC分类号： H01L21/768 , H01L23/535 , H01L23/532
摘要： A barrier layer is formed in a portion of a thickness of sidewalls in a recess prior to formation of an interconnect structure in the recess. The barrier layer is formed in the portion of the thickness of the sidewalls by a plasma-based deposition operation, in which a precursor reacts with a silicon-rich surface to form the barrier layer. The barrier layer is formed in the portion of the thickness of the sidewalls in that the precursor consumes a portion of the silicon-rich surface of the sidewalls as a result of the plasma treatment. This enables the barrier layer to be formed in a manner in which the cross-sectional width reduction in the recess from the barrier layer is minimized while enabling the barrier layer to be used to promote adhesion in the recess.
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公开(公告)号：US20230260847A1
公开(公告)日：2023-08-17
申请号：US18308952
申请日：2023-04-28
发明人： Wei-Yip LOH , Yan-Ming TSAI , Yi-Ning TAI , Raghunath PUTIKAM , Hung-Yi HUANG , Hung-Hsu CHEN , Chih-Wei CHANG
IPC分类号： H01L21/8238 , H01L29/40
CPC分类号： H01L21/823814 , H01L29/401 , H01L21/823821 , H01L21/823871 , H01L29/41791
摘要： Techniques described herein enable respective (different) types of metal silicide layers to be formed for p-type source/drain regions and n-type source/drain regions in a selective manner. For example, a p-type metal silicide layer may be selectively formed over a p-type source/drain region (e.g., such that the p-type metal silicide layer is not formed over the n-type source/drain region) and an n-type metal silicide layer may be formed over the n-type source/drain region (which may be selective or non-selective). This provides a low Schottky barrier height between the p-type metal silicide layer and the p-type source/drain region, as well as a low Schottky barrier height between the n-type metal silicide layer and the n-type source/drain region. This reduces the contact resistance for both p-type source/drain regions and n-type source/drain regions.
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公开(公告)号：US20230230916A1
公开(公告)日：2023-07-20
申请号：US17577800
申请日：2022-01-18
发明人： Shuen-Shin LIANG , Chia-Hung CHU , Po-Chin CHANG , Tzu-Pei CHEN , Ken-Yu CHANG , Hung-Yi HUANG , Harry CHIEN , Wei-Yip LOH , Chun-I TSAI , Hong-Mao LEE , Sung-Li WANG , Pinyen LIN
IPC分类号： H01L23/522 , H01L29/40 , H01L21/768
CPC分类号： H01L23/5226 , H01L29/401 , H01L21/76877 , H01L21/76843
摘要： A method for manufacturing a semiconductor device includes: forming a lower metal contact in a trench of a first dielectric structure, the lower metal contact having a height less than a depth of the trench and being made of a first metal material; forming an upper metal contact to fill the trench and to be in contact with the lower metal contact, the upper metal contact being formed of a second metal material different from the first metal material and having a bottom surface with a dimension the same as a dimension of a top surface of the lower metal contact; forming a second dielectric structure on the first dielectric structure; and forming a via contact penetrating through the second dielectric structure to be electrically connected to the upper metal contact, the via contact being formed of a metal material the same as the second metal material.
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公开(公告)号：US20220367194A1
公开(公告)日：2022-11-17
申请号：US17491161
申请日：2021-09-30
发明人： Min-Hsuan LU , Kan-Ju LIN , Lin-Yu HUANG , Sheng-Tsung WANG , Hung-Yi HUANG , Chih-Wei CHANG , Ming-Hsing TSAI , Chih-Hao WANG
IPC分类号： H01L21/285 , H01L29/40 , C23C16/42
摘要： In a semiconductor structure, a first conductive feature is formed in a trench by PVD and a glue layer is then deposited on the first conductive feature in the trench before CVD deposition of a second conductive feature there-over. The first conductive feature acts as a protection layer to keep silicide from being damaged by later deposition of metal or a precursor by CVD. The glue layer extends along the extent of the sidewall to enhance the adhesion of the second conductive features to the surrounding dielectric layer.
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公开(公告)号：US20240355741A1
公开(公告)日：2024-10-24
申请号：US18760444
申请日：2024-07-01
发明人： Shuen-Shin LIANG , Chun-I TSAI , Chih-Wei CHANG , Chun-Hsien HUANG , Hung-Yi HUANG , Keng-Chu LIN , Ken-Yu CHANG , Sung-Li WANG , Chia-Hung CHU , Hsu-Kai CHANG
IPC分类号： H01L23/532 , H01L21/285 , H01L21/768 , H01L23/522
CPC分类号： H01L23/53266 , H01L21/76802 , H01L21/7685 , H01L21/28568 , H01L21/76843 , H01L23/5226
摘要： The present disclosure describes a method for forming capping layers configured to prevent the migration of out-diffused cobalt atoms into upper metallization layers In some embodiments, the method includes depositing a cobalt diffusion barrier layer on a liner-free conductive structure that includes ruthenium, where depositing the cobalt diffusion barrier layer includes forming the cobalt diffusion barrier layer self-aligned to the liner-free conductive structure. The method also includes depositing, on the cobalt diffusion barrier layer, a stack with an etch stop layer and dielectric layer, and forming an opening in the stack to expose the cobalt diffusion barrier layer. Finally, the method includes forming a conductive structure on the cobalt diffusion barrier layer.
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