公开(公告)号：US20250063758A1

公开(公告)日：2025-02-20

申请号：US18937604

申请日：2024-11-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Cheng-Wei CHANG ,  Chia-Hung CHU ,  Hsu-Kai CHANG ,  Sung-Li WANG ,  Kuan-Kan HU ,  Shuen-Shin LIANG ,  Kao-Feng LIN ,  Hung Pin LU ,  Yi-Ying LIU ,  Chuan-Hui SHEN

IPC: H01L29/78 ,  H01L21/285 ,  H01L21/768 ,  H01L29/40 ,  H01L29/417

Abstract: A titanium precursor is used to selectively form a titanium silicide (TiSix) layer in a semiconductor device. A plasma-based deposition operation is performed in which the titanium precursor is provided into an opening, and a reactant gas and a plasma are used to cause silicon to diffuse to a top surface of a transistor structure. The diffusion of silicon results in the formation of a silicon-rich surface of the transistor structure, which increases the selectivity of the titanium silicide formation relative to other materials of the semiconductor device. The titanium precursor reacts with the silicon-rich surface to form the titanium silicide layer. The selective titanium silicide layer formation results in the formation of a titanium silicon nitride (TiSixNy) on the sidewalls in the opening, which enables a conductive structure such as a metal source/drain contact to be formed in the opening without the addition of another barrier layer.

公开(公告)号：US20240405023A1

公开(公告)日：2024-12-05

申请号：US18326241

申请日：2023-05-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shuen-Shin LIANG ,  Hong-Mao Lee ,  Sung-Li Wang ,  Yan-Ming Tsai ,  Po-Chin Chang ,  Wei-Yip Loh ,  Harry CHIEN ,  Pei-Hua Lee

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/40 ,  H01L29/45 ,  H01L29/66

Abstract: A semiconductor device includes a semiconductor fin protruding from a substrate. The semiconductor device includes a P-type device over the semiconductor fin and an N-type device over the semiconductor fin. The P-type device includes a first source/drain (S/D) feature adjacent a first gate structure. The P-type device includes a dipole layer over the first S/D feature, where the dipole layer includes a first metal and a second metal different from the first metal. The P-type device further includes a first silicide layer over the dipole layer, where the first silicide layer includes the first metal. The N-type device includes a second S/D feature adjacent a second gate structure. The N-type device further includes a second silicide layer directly contacting the second S/D feature, where the second silicide layer includes the first metal, and where a composition of the second silicide layer is different from that of the dipole layer.

公开(公告)号：US20230402366A1

公开(公告)日：2023-12-14

申请号：US17836781

申请日：2022-06-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shuen-Shin LIANG ,  Chia-Hung CHU ,  Po-Chin CHANG ,  Hsu-Kai CHANG ,  Kuan-Kan HU ,  Ken-Yu CHANG ,  Hung-Yi HUANG ,  Harry CHIEN ,  Wei-Yip LOH ,  Chun-I TSAI ,  Hong-Mao LEE ,  Sung-Li WANG ,  Pinyen LIN ,  Chuan-Hui SHEN

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L23/53266 ,  H01L21/76843 ,  H01L21/76883

Abstract: A semiconductor device includes a substrate, a source/drain region disposed in the substrate, a silicide structure disposed on the source/drain region, a first dielectric layer disposed over the substrate, a conductive contact disposed in the first dielectric layer and over the silicide structure, a second dielectric layer disposed over the first dielectric layer, a via contact disposed in the second dielectric layer and connected to the conductive contact, and a first metal surrounding the via contact.

公开(公告)号：US20220375868A1

公开(公告)日：2022-11-24

申请号：US17875242

申请日：2022-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Cheng-Wei CHANG ,  Chia-Hung CHU ,  Kao-Feng LIN ,  Hsu-Kai CHANG ,  Shuen-Shin LIANG ,  Sung-Li WANG ,  Yi-Ying LIU ,  Po-Nan YEH ,  Yu Shih WANG ,  U-Ting CHIU ,  Chun-Neng LIN ,  Ming-Hsi YEH

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768

Abstract: A semiconductor device includes a gate electrode, a source/drain structure, a lower contact contacting either of the gate electrode or the source/drain structure, and an upper contact disposed in an opening formed in an interlayer dielectric (ILD) layer and in direct contact with the lower contact. The upper contact is in direct contact with the ILD layer without an interposing conductive barrier layer, and the upper contact includes ruthenium.

公开(公告)号：US20220336655A1

公开(公告)日：2022-10-20

申请号：US17855992

申请日：2022-07-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shuen-Shin LIANG ,  Pang-Yen TSAI ,  Keng-Chu LIN ,  Sung-Li WANG ,  Pinyen LIN

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first semiconductor nanostructure and a second semiconductor nanostructure stacked over a substrate. The semiconductor device structure also includes a first epitaxial structure connecting the first semiconductor nanostructure and a second epitaxial structure connecting the second semiconductor nanostructure. The semiconductor device structure further includes a gate stack wrapped around the first semiconductor nanostructure and the second semiconductor nanostructure. In addition, the semiconductor device structure includes a conductive contact electrically connected to the epitaxial structures. The conductive contact has a portion extending towards the gate stack from terminals of the first epitaxial structure and the second epitaxial structures. The first epitaxial structure is wider than the portion of the conductive contact.

公开(公告)号：US20240055485A1

公开(公告)日：2024-02-15

申请号：US17886797

申请日：2022-08-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Cheng-Wei CHANG ,  Shahaji B. MORE ,  Shuen-Shin LIANG ,  Sung-Li WANG ,  Yi-Ying LIU

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/786 ,  H01L29/775 ,  H01L21/285 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/78696 ,  H01L29/775 ,  H01L21/28518 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66439

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a source/drain epitaxial feature disposed over a substrate, wherein the source/drain epitaxial feature comprises a first epitaxial layer, a second epitaxial layer in contact with the first epitaxial layer, wherein the second epitaxial layer has a first dopant concentration, and a third epitaxial layer having sidewalls enclosed by the second epitaxial layer, wherein the third epitaxial layer has a second dopant concentration higher than the first dopant concentration. The semiconductor device structure also includes a source/drain cap layer disposed above and in contact with the second epitaxial layer and the third epitaxial layer, wherein the source/drain cap layer has a third dopant concentration higher than the second dopant concentration, and a silicide layer disposed above and in contact with the source/drain cap layer.

公开(公告)号：US20230387316A1

公开(公告)日：2023-11-30

申请号：US17825516

申请日：2022-05-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shuen-Shin LIANG ,  Min-Chiang CHUANG ,  Chia-Cheng CHEN ,  Chun-Hung WU ,  Liang-Yin CHEN ,  Sung-Li WANG ,  Pinyen LIN ,  Kuan-Kan HU ,  Jhih-Rong HUANG ,  Szu-Hsian LEE ,  Tsun-Jen CHAN ,  Cheng-Wei LIAN ,  Po-Chin CHANG ,  Chuan-Hui SHEN ,  Lin-Yu HUANG ,  Yuting CHENG ,  Yan-Ming TSAI ,  Hong-Mao LEE

IPC: H01L29/786 ,  H01L29/417

CPC classification number: H01L29/78651 ,  H01L29/41733

Abstract: A semiconductor device includes a source/drain portion, a metal silicide layer disposed over the source/drain portion, and a transition layer disposed between the source/drain portion and the metal silicide layer. The transition layer includes implantation elements, and an atomic concentration of the implantation elements in the transition layer is higher than that in each of the source/drain portion and the metal silicide layer so as to reduce a contact resistance between the source/drain portion and the metal silicide layer. Methods for manufacturing the semiconductor device are also disclosed.

公开(公告)号：US20230230916A1

公开(公告)日：2023-07-20

申请号：US17577800

申请日：2022-01-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shuen-Shin LIANG ,  Chia-Hung CHU ,  Po-Chin CHANG ,  Tzu-Pei CHEN ,  Ken-Yu CHANG ,  Hung-Yi HUANG ,  Harry CHIEN ,  Wei-Yip LOH ,  Chun-I TSAI ,  Hong-Mao LEE ,  Sung-Li WANG ,  Pinyen LIN

IPC: H01L23/522 ,  H01L29/40 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L29/401 ,  H01L21/76877 ,  H01L21/76843

Abstract: A method for manufacturing a semiconductor device includes: forming a lower metal contact in a trench of a first dielectric structure, the lower metal contact having a height less than a depth of the trench and being made of a first metal material; forming an upper metal contact to fill the trench and to be in contact with the lower metal contact, the upper metal contact being formed of a second metal material different from the first metal material and having a bottom surface with a dimension the same as a dimension of a top surface of the lower metal contact; forming a second dielectric structure on the first dielectric structure; and forming a via contact penetrating through the second dielectric structure to be electrically connected to the upper metal contact, the via contact being formed of a metal material the same as the second metal material.

公开(公告)号：US20240332393A1

公开(公告)日：2024-10-03

申请号：US18741963

申请日：2024-06-13

Applicant: Taiwan Semiconductor Manufacturing Company, LTD.

Inventor： Hsu-Kai CHANG ,  Jhih-Rong HUANG ,  Yen-Tien TUNG ,  Chia-Hung CHU ,  Shuen-Shin LIANG ,  Tzer-Min SHEN ,  Pinyen LIN ,  Sung-Li WANG

IPC: H01L29/45 ,  H01L21/285 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/45 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second gate structures disposed on first and second fin structures, first and second source/drain (S/D) regions disposed on the first and second fin structures, first and second contact structures disposed on the first and second S/D regions, and a dipole layer disposed at an interface between the first nWFM silicide layer and the first S/D region. The first contact structure includes a first nWFM silicide layer disposed on the first S/D region and a first contact plug disposed on the first nWFM silicide layer. The second contact structure includes a pWFM silicide layer disposed on the second S/D region, a second nWFM silicide layer disposed on the pWFM silicide layer, and a second contact plug disposed on the pWFM silicide layer.

公开(公告)号：US20240313075A1

公开(公告)日：2024-09-19

申请号：US18182921

申请日：2023-03-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shuen-Shin LIANG ,  Kan-Ju LIN ,  Chia-Hung CHU ,  Chien CHANG ,  Harry CHIEN ,  Sung-Li WANG

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: The present disclosure provides a method for semiconductor fabrication. The method includes depositing a first metal layer by a first deposition over a source/drain (S/D) feature and over side portions of a trench exposing the S/D feature. The first metal layer is thicker over the S/D feature than over side portions of the trench. The method includes growing a metal on the first metal layer by a second deposition to form a second metal layer filling up the trench. The second deposition is different from the first deposition and the growing of the metal in a vertical direction is grown at a faster rate than the growing of the metal in a horizontal direction. After growing the metal to form the second metal layer, the method includes planarizing the first and second metal layers to form an S/D contact. The method forms an S/D via on the second metal layer.