公开(公告)号：US20230387316A1

公开(公告)日：2023-11-30

申请号：US17825516

申请日：2022-05-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shuen-Shin LIANG ,  Min-Chiang CHUANG ,  Chia-Cheng CHEN ,  Chun-Hung WU ,  Liang-Yin CHEN ,  Sung-Li WANG ,  Pinyen LIN ,  Kuan-Kan HU ,  Jhih-Rong HUANG ,  Szu-Hsian LEE ,  Tsun-Jen CHAN ,  Cheng-Wei LIAN ,  Po-Chin CHANG ,  Chuan-Hui SHEN ,  Lin-Yu HUANG ,  Yuting CHENG ,  Yan-Ming TSAI ,  Hong-Mao LEE

IPC分类号： H01L29/786 ,  H01L29/417

CPC分类号： H01L29/78651 ,  H01L29/41733

摘要： A semiconductor device includes a source/drain portion, a metal silicide layer disposed over the source/drain portion, and a transition layer disposed between the source/drain portion and the metal silicide layer. The transition layer includes implantation elements, and an atomic concentration of the implantation elements in the transition layer is higher than that in each of the source/drain portion and the metal silicide layer so as to reduce a contact resistance between the source/drain portion and the metal silicide layer. Methods for manufacturing the semiconductor device are also disclosed.

公开(公告)号：US20220310595A1

公开(公告)日：2022-09-29

申请号：US17839054

申请日：2022-06-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Wei LIN ,  Chih-Lin WANG ,  Kang-Min KUO ,  Cheng-Wei LIAN

IPC分类号： H01L27/092 ,  H01L29/49 ,  H01L29/51 ,  H01L29/40 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66

摘要： Semiconductor structures and methods for forming the same are provided. The method includes forming a dummy gate structure over a substrate and forming a sealing layer surrounding the dummy gate structure. The method includes forming a spacer covering the sealing layer and removing the dummy gate structure to form a trench. The method further includes forming an interfacial layer and a gate dielectric layer. The method further includes forming a capping layer over the gate dielectric layer and partially oxidizing the capping layer to form a capping oxide layer. The method further includes forming a work function metal layer over the capping oxide layer and forming a gate electrode layer over the work function metal layer. In addition, a bottom surface of the capping oxide layer is higher than a bottom surface of the spacer.