公开(公告)号：US20240379759A1

公开(公告)日：2024-11-14

申请号：US18314968

申请日：2023-05-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wei-Yip LOH ,  Li-Wei CHU ,  Hong-Mao LEE ,  Hung-Chang HSU ,  Hung-Hsu CHEN ,  Harry CHIEN ,  Chih-Wei CHANG

IPC: H01L29/08 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device includes a first transistor, a second transistor, a first metal silicide layer, a second metal silicide layer, and an isolation structure. The first transistor includes a first channel layer, a first gate structure, and first source/drain epitaxy structures. The second transistor includes a second channel layer, a second gate structure, and second source/drain epitaxy structures. The first metal silicide layer is over one of the first source/drain epitaxy structures. The second metal silicide layer is over one of the second source/drain epitaxy structures. The isolation structure covers the one of the first source/drain epitaxy structures and the one of the second source/drain epitaxy structures, wherein in a cross-sectional view, the one of the first source/drain epitaxy structures is separated from the isolation structure through the first metal silicide layer, while the one of the second source/drain epitaxy structures is in contact with the isolation structure.

公开(公告)号：US20230387316A1

公开(公告)日：2023-11-30

申请号：US17825516

申请日：2022-05-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shuen-Shin LIANG ,  Min-Chiang CHUANG ,  Chia-Cheng CHEN ,  Chun-Hung WU ,  Liang-Yin CHEN ,  Sung-Li WANG ,  Pinyen LIN ,  Kuan-Kan HU ,  Jhih-Rong HUANG ,  Szu-Hsian LEE ,  Tsun-Jen CHAN ,  Cheng-Wei LIAN ,  Po-Chin CHANG ,  Chuan-Hui SHEN ,  Lin-Yu HUANG ,  Yuting CHENG ,  Yan-Ming TSAI ,  Hong-Mao LEE

IPC: H01L29/786 ,  H01L29/417

CPC classification number: H01L29/78651 ,  H01L29/41733

Abstract: A semiconductor device includes a source/drain portion, a metal silicide layer disposed over the source/drain portion, and a transition layer disposed between the source/drain portion and the metal silicide layer. The transition layer includes implantation elements, and an atomic concentration of the implantation elements in the transition layer is higher than that in each of the source/drain portion and the metal silicide layer so as to reduce a contact resistance between the source/drain portion and the metal silicide layer. Methods for manufacturing the semiconductor device are also disclosed.

公开(公告)号：US20230230916A1

公开(公告)日：2023-07-20

申请号：US17577800

申请日：2022-01-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shuen-Shin LIANG ,  Chia-Hung CHU ,  Po-Chin CHANG ,  Tzu-Pei CHEN ,  Ken-Yu CHANG ,  Hung-Yi HUANG ,  Harry CHIEN ,  Wei-Yip LOH ,  Chun-I TSAI ,  Hong-Mao LEE ,  Sung-Li WANG ,  Pinyen LIN

IPC: H01L23/522 ,  H01L29/40 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L29/401 ,  H01L21/76877 ,  H01L21/76843

Abstract: A method for manufacturing a semiconductor device includes: forming a lower metal contact in a trench of a first dielectric structure, the lower metal contact having a height less than a depth of the trench and being made of a first metal material; forming an upper metal contact to fill the trench and to be in contact with the lower metal contact, the upper metal contact being formed of a second metal material different from the first metal material and having a bottom surface with a dimension the same as a dimension of a top surface of the lower metal contact; forming a second dielectric structure on the first dielectric structure; and forming a via contact penetrating through the second dielectric structure to be electrically connected to the upper metal contact, the via contact being formed of a metal material the same as the second metal material.

公开(公告)号：US20240379758A1

公开(公告)日：2024-11-14

申请号：US18196223

申请日：2023-05-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wei-Yip LOH ,  Hong-Mao LEE ,  Harry CHIEN ,  Po-Chin CHANG ,  Sung-Li WANG ,  Jhih-Rong HUANG ,  Tzer-Min SHEN ,  Chih-Wei CHANG

IPC: H01L29/08 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/20 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device structure and methods of forming the same are described. In some embodiments, the structure includes an N-type source/drain epitaxial feature disposed over a substrate, a P-type source/drain epitaxial feature disposed over the substrate, a first silicide layer disposed directly on the N-type source/drain epitaxial feature, and a second silicide layer disposed directly on the P-type source/drain epitaxial feature. The first and second silicide layers include a first metal, and the second silicide layer is substantially thicker than the first silicide layer. The structure further includes a third silicide layer disposed directly on the first silicide layer and a fourth silicide layer disposed directly on the second silicide layer. The third and fourth silicide layer include a second metal different from the first metal, and the third silicide layer is substantially thicker than the fourth silicide layer.

公开(公告)号：US20230411496A1

公开(公告)日：2023-12-21

申请号：US17750996

申请日：2022-05-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Kan-Ju LIN ,  Chien CHANG ,  Chih-Shiun CHOU ,  Tai Min CHANG ,  Yi-Ning TAI ,  Hong-Mao LEE ,  Yan-Ming TSAI ,  Wei-Yip LOH ,  Harry CHIEN ,  Chih-Wei CHANG ,  Ming-Hsing TSAI ,  Lin-Yu HUANG

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L29/7851 ,  H01L29/41791 ,  H01L21/823418

Abstract: A semiconductor structure and method of forming a semiconductor structure are provided. In some embodiments, the method includes forming a gate structure over a substrate. An epitaxial source/drain region is formed adjacent to the gate structure. A dielectric layer is formed over the epitaxial source/drain region. An opening is formed, the opening extending through the dielectric layer and exposing the epitaxial source/drain region. Sidewalls of the opening are defined by the dielectric layer and a bottom of the opening is defined by the epitaxial source/drain region. A silicide layer is formed on the epitaxial source/drain region. A metal capping layer including tungsten, molybdenum, or a combination thereof is selectively formed on the silicide layer by a first deposition process. The opening is filled with a first conductive material in a bottom-up manner from the metal capping layer by a second deposition process different from the first deposition process.

公开(公告)号：US20230402366A1

公开(公告)日：2023-12-14

申请号：US17836781

申请日：2022-06-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shuen-Shin LIANG ,  Chia-Hung CHU ,  Po-Chin CHANG ,  Hsu-Kai CHANG ,  Kuan-Kan HU ,  Ken-Yu CHANG ,  Hung-Yi HUANG ,  Harry CHIEN ,  Wei-Yip LOH ,  Chun-I TSAI ,  Hong-Mao LEE ,  Sung-Li WANG ,  Pinyen LIN ,  Chuan-Hui SHEN

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L23/53266 ,  H01L21/76843 ,  H01L21/76883

Abstract: A semiconductor device includes a substrate, a source/drain region disposed in the substrate, a silicide structure disposed on the source/drain region, a first dielectric layer disposed over the substrate, a conductive contact disposed in the first dielectric layer and over the silicide structure, a second dielectric layer disposed over the first dielectric layer, a via contact disposed in the second dielectric layer and connected to the conductive contact, and a first metal surrounding the via contact.