公开(公告)号：US20230395429A1

公开(公告)日：2023-12-07

申请号：US17805605

申请日：2022-06-06

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kan-Ju LIN ,  Hao-Heng LIU ,  Chien CHANG ,  Hung-Yi HUANG ,  Harry CHIEN

IPC分类号： H01L21/768 ,  H01L23/522 ,  C23C16/56 ,  C23C16/14

CPC分类号： H01L21/76876 ,  H01L21/76873 ,  H01L21/76843 ,  H01L21/76865 ,  H01L23/5226 ,  C23C16/56 ,  C23C16/14 ,  H01L23/53223

摘要： Depositing a seed layer after formation of the MD in order to reduce or prevent epitaxial growth of the seed layer toward the MD. For example, the seed layer may be deposited using CVD and conformal dry etching. In some implementations, the seed layer may be formed of ruthenium (Ru), molybdenum (Mo), or tungsten (W). Accordingly, the seed layer helps reduce or prevent seam formation in the VG, which reduces resistance of the VG by allowing for bottom-up metal growth. Additionally, current leakage from the VG to the MD is reduced or even prevented. As a result, device performance and efficiency are increased and breakdown voltage of the gate structure is also increased. Additionally, because electrical shorts are less likely, yield is increased, which conserves power, raw materials, and processing resources that otherwise would have been consumed during manufacture.

公开(公告)号：US20240312901A1

公开(公告)日：2024-09-19

申请号：US18220886

申请日：2023-07-12

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chien CHANG ,  Yen-Chun LIN ,  Jen-Wei LIU ,  Chih-Han TSENG ,  Harry CHIEN ,  Cheng-Hui WENG ,  Chun-Chieh LIN ,  Hung-Wen SU ,  Ming-Hsing TSAI ,  Chih-Wei CHANG

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L23/532 ,  H01L29/417

CPC分类号： H01L23/5226 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/7685 ,  H01L21/76877 ,  H01L23/53238 ,  H01L29/41725

摘要： An interconnect structure including a contact via in an interlayer dielectric, a first conductive feature in a first dielectric layer, the first dielectric layer over the interlayer dielectric, a first liner in the first dielectric layer, the first liner comprising a first part in contact with a sidewall surface of the first conductive feature, and a second part in contact with a bottom surface of the first conductive feature. The interconnect structure includes a first cap layer in contact with a top surface of the first conductive feature, a second conductive feature in a second dielectric layer, the second dielectric layer over the first dielectric layer, a second liner in the second dielectric layer, wherein the first and second conductive features comprise a first conductive material, and the contact via, first liner, first cap layer, and second liner comprise a second conductive material chemically different than the first conductive material.

公开(公告)号：US20230411496A1

公开(公告)日：2023-12-21

申请号：US17750996

申请日：2022-05-23

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Kan-Ju LIN ,  Chien CHANG ,  Chih-Shiun CHOU ,  Tai Min CHANG ,  Yi-Ning TAI ,  Hong-Mao LEE ,  Yan-Ming TSAI ,  Wei-Yip LOH ,  Harry CHIEN ,  Chih-Wei CHANG ,  Ming-Hsing TSAI ,  Lin-Yu HUANG

IPC分类号： H01L29/66 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/78

CPC分类号： H01L29/66795 ,  H01L29/7851 ,  H01L29/41791 ,  H01L21/823418

摘要： A semiconductor structure and method of forming a semiconductor structure are provided. In some embodiments, the method includes forming a gate structure over a substrate. An epitaxial source/drain region is formed adjacent to the gate structure. A dielectric layer is formed over the epitaxial source/drain region. An opening is formed, the opening extending through the dielectric layer and exposing the epitaxial source/drain region. Sidewalls of the opening are defined by the dielectric layer and a bottom of the opening is defined by the epitaxial source/drain region. A silicide layer is formed on the epitaxial source/drain region. A metal capping layer including tungsten, molybdenum, or a combination thereof is selectively formed on the silicide layer by a first deposition process. The opening is filled with a first conductive material in a bottom-up manner from the metal capping layer by a second deposition process different from the first deposition process.

公开(公告)号：US20240313075A1

公开(公告)日：2024-09-19

申请号：US18182921

申请日：2023-03-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shuen-Shin LIANG ,  Kan-Ju LIN ,  Chia-Hung CHU ,  Chien CHANG ,  Harry CHIEN ,  Sung-Li WANG

IPC分类号： H01L29/423 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L29/42392 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

摘要： The present disclosure provides a method for semiconductor fabrication. The method includes depositing a first metal layer by a first deposition over a source/drain (S/D) feature and over side portions of a trench exposing the S/D feature. The first metal layer is thicker over the S/D feature than over side portions of the trench. The method includes growing a metal on the first metal layer by a second deposition to form a second metal layer filling up the trench. The second deposition is different from the first deposition and the growing of the metal in a vertical direction is grown at a faster rate than the growing of the metal in a horizontal direction. After growing the metal to form the second metal layer, the method includes planarizing the first and second metal layers to form an S/D contact. The method forms an S/D via on the second metal layer.

公开(公告)号：US20230008239A1

公开(公告)日：2023-01-12

申请号：US17658901

申请日：2022-04-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chien CHANG ,  Min-Hsiu HUNG ,  Yu-Hsiang LIAO ,  Yu-Shiuan WANG ,  Tai Min CHANG ,  Kan-Ju LIN ,  Chih-Shiun CHOU ,  Hung-Yi HUANG ,  Chih-Wei CHANG ,  Ming-Hsing TSAI

IPC分类号： H01L21/768 ,  H01L23/535 ,  H01L23/532

摘要： A barrier layer is formed in a portion of a thickness of sidewalls in a recess prior to formation of an interconnect structure in the recess. The barrier layer is formed in the portion of the thickness of the sidewalls by a plasma-based deposition operation, in which a precursor reacts with a silicon-rich surface to form the barrier layer. The barrier layer is formed in the portion of the thickness of the sidewalls in that the precursor consumes a portion of the silicon-rich surface of the sidewalls as a result of the plasma treatment. This enables the barrier layer to be formed in a manner in which the cross-sectional width reduction in the recess from the barrier layer is minimized while enabling the barrier layer to be used to promote adhesion in the recess.