公开(公告)号：US20230008239A1

公开(公告)日：2023-01-12

申请号：US17658901

申请日：2022-04-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chien CHANG ,  Min-Hsiu HUNG ,  Yu-Hsiang LIAO ,  Yu-Shiuan WANG ,  Tai Min CHANG ,  Kan-Ju LIN ,  Chih-Shiun CHOU ,  Hung-Yi HUANG ,  Chih-Wei CHANG ,  Ming-Hsing TSAI

IPC分类号： H01L21/768 ,  H01L23/535 ,  H01L23/532

摘要： A barrier layer is formed in a portion of a thickness of sidewalls in a recess prior to formation of an interconnect structure in the recess. The barrier layer is formed in the portion of the thickness of the sidewalls by a plasma-based deposition operation, in which a precursor reacts with a silicon-rich surface to form the barrier layer. The barrier layer is formed in the portion of the thickness of the sidewalls in that the precursor consumes a portion of the silicon-rich surface of the sidewalls as a result of the plasma treatment. This enables the barrier layer to be formed in a manner in which the cross-sectional width reduction in the recess from the barrier layer is minimized while enabling the barrier layer to be used to promote adhesion in the recess.

公开(公告)号：US20230411496A1

公开(公告)日：2023-12-21

申请号：US17750996

申请日：2022-05-23

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Kan-Ju LIN ,  Chien CHANG ,  Chih-Shiun CHOU ,  Tai Min CHANG ,  Yi-Ning TAI ,  Hong-Mao LEE ,  Yan-Ming TSAI ,  Wei-Yip LOH ,  Harry CHIEN ,  Chih-Wei CHANG ,  Ming-Hsing TSAI ,  Lin-Yu HUANG

IPC分类号： H01L29/66 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/78

CPC分类号： H01L29/66795 ,  H01L29/7851 ,  H01L29/41791 ,  H01L21/823418

摘要： A semiconductor structure and method of forming a semiconductor structure are provided. In some embodiments, the method includes forming a gate structure over a substrate. An epitaxial source/drain region is formed adjacent to the gate structure. A dielectric layer is formed over the epitaxial source/drain region. An opening is formed, the opening extending through the dielectric layer and exposing the epitaxial source/drain region. Sidewalls of the opening are defined by the dielectric layer and a bottom of the opening is defined by the epitaxial source/drain region. A silicide layer is formed on the epitaxial source/drain region. A metal capping layer including tungsten, molybdenum, or a combination thereof is selectively formed on the silicide layer by a first deposition process. The opening is filled with a first conductive material in a bottom-up manner from the metal capping layer by a second deposition process different from the first deposition process.