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公开(公告)号:US20240355742A1
公开(公告)日:2024-10-24
申请号:US18760471
申请日:2024-07-01
发明人: Cheng-Wei Chang , Chien-Shun Liao , Sung-Li Wang , Shuen-Shin Liang , Shu-Lan Chang , Yi-Ying Liu , Chia-Hung Chu , Hsu-Kai Chang
IPC分类号: H01L23/532 , H01L21/768 , H01L23/528
CPC分类号: H01L23/53266 , H01L21/76816 , H01L21/7684 , H01L21/76883 , H01L23/5283 , H01L23/53238
摘要: The present disclosure describes a method for the fabrication of ruthenium conductive structures over cobalt conductive structures. In some embodiments, the method includes forming a first opening in a dielectric layer to expose a first cobalt contact and filling the first opening with ruthenium metal to form a ruthenium contact on the first cobalt contact. The method also includes forming a second opening in the dielectric layer to expose a second cobalt contact and a gate structure and filling the second opening with tungsten to form a tungsten contact on the second cobalt contact and the gate structure. Further, the method includes forming a copper conductive structure on the ruthenium contact and the tungsten contact, where the copper from the copper conductive structure is in contact with the ruthenium metal from the ruthenium contact.
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公开(公告)号:US11894438B2
公开(公告)日:2024-02-06
申请号:US17353460
申请日:2021-06-21
发明人: Yee-Chia Yeo , Sung-Li Wang , Chi On Chui , Jyh-Cherng Sheu , Hung-Li Chiang , I-Sheng Chen
IPC分类号: H01L29/45 , H01L21/8238 , H01L27/092 , H01L21/8234 , H01L23/522 , H01L27/088 , H01L29/08 , H01L29/417 , H01L29/78
CPC分类号: H01L29/45 , H01L21/823425 , H01L21/823814 , H01L21/823821 , H01L23/5226 , H01L27/0886 , H01L27/092 , H01L27/0924 , H01L29/0847 , H01L29/41791 , H01L29/7851 , H01L21/823807 , H01L29/456 , H01L2029/7858
摘要: A semiconductor device includes a field effect transistor (FET). The FET includes a first channel, a first source and a first drain; a second channel, a second source and a second drain; and a gate structure disposed over the first and second channels. The gate structure includes a gate dielectric layer and a gate electrode layer. The first source includes a first crystal semiconductor layer and the second source includes a second crystal semiconductor layer. The first source and the second source are connected by an alloy layer made of one or more Group IV element and one or more transition metal elements. The first crystal semiconductor layer is not in direct contact with the second crystal semiconductor layer.
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公开(公告)号:US11031300B2
公开(公告)日:2021-06-08
申请号:US16251841
申请日:2019-01-18
发明人: Sung-Li Wang , Peng-Wei Chu , Yasutoshi Okuno
IPC分类号: H01L21/8238 , H01L27/092 , H01L29/66 , H01L21/324 , H01L29/08 , H01L21/02 , H01L29/78
摘要: A method for manufacturing a semiconductor structure is provided. The method includes: receiving a substrate having a first epitaxy region in a first transistor of a first conductive type and a second epitaxy region in a second transistor of a second conductive type; introducing an agent onto the first epitaxy region and the second epitaxy region, wherein the agent is selectively deposited to the second epitaxy region; selectively depositing a first metal layer on the first epitaxy region; and depositing a second metal layer on the first epitaxy region and the second epitaxy region. A semiconductor structure according to the method is also provided.
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公开(公告)号:US20210083119A1
公开(公告)日:2021-03-18
申请号:US16572812
申请日:2019-09-17
发明人: Mrunal A. Khaderbad , Keng-Chu Lin , Sung-Li Wang
IPC分类号: H01L29/78 , H01L21/768 , H01L29/417 , H01L29/66
摘要: A structure includes a transistor including a first source/drain region, a source/drain contact plug over and electrically coupling to the first source/drain region, and a via over and contacting the source/drain contact plug. The via has a bottom portion having a first length, and an upper portion having a second length. The first length is greater than the second length. Both of the first length and the second length are measured in a same direction parallel to a top surface of the source/drain contact plug.
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公开(公告)号:US20200258746A1
公开(公告)日:2020-08-13
申请号:US16859125
申请日:2020-04-27
发明人: Sung-Li Wang , Jyh-Cherng Sheu , Huang-Yi Huang , Chih-Wei Chang , Chi On Chui
IPC分类号: H01L21/285 , H01L21/321 , H01L29/417 , H01L21/02 , H01L21/3205 , H01L21/3213 , H01L21/768 , H01L23/535 , H01L29/08 , H01L29/66 , H01L29/78
摘要: A method includes forming a source/drain region, and in a vacuum chamber or a vacuum cluster system, preforming a selective deposition to form a metal silicide layer on the source/drain region, and a metal layer on dielectric regions adjacent to the source/drain region. The method further includes selectively etching the metal layer in the vacuum chamber, and selectively forming a metal nitride layer on the metal silicide layer. The selectively forming the metal nitride layer is performed in the vacuum chamber or a vacuum cluster system without vacuum break.
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公开(公告)号:US20200006224A1
公开(公告)日:2020-01-02
申请号:US16569912
申请日:2019-09-13
发明人: Sung-Li Wang , Yasutoshi Okuno
IPC分类号: H01L23/522 , H01L23/528 , H01L21/768
摘要: Embodiments described herein relate generally to one or more methods for forming an interconnect structure, such as a dual damascene interconnect structure comprising a conductive line and a conductive via, and structures formed thereby. In some embodiments, an interconnect opening is formed through one or more dielectric layers over a semiconductor substrate. The interconnect opening has a via opening and a trench over the via opening. A conductive via is formed in the via opening. A nucleation enhancement treatment is performed on one or more exposed dielectric surfaces of the trench. A conductive line is formed in the trench on the one or more exposed dielectric surfaces of the trench and on the conductive via.
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公开(公告)号:US20190214296A1
公开(公告)日:2019-07-11
申请号:US16354362
申请日:2019-03-15
发明人: Sung-Li Wang , Shuen-Shin Liang , Jung-Hao Chang , Chia-Hung Chu , Keng-Chu Lin
IPC分类号: H01L21/768
CPC分类号: H01L21/76814 , H01L21/76847 , H01L21/76879 , H01L21/76883
摘要: Embodiments described herein relate generally to one or more methods for forming an interconnect structure, such as a dual damascene interconnect structure comprising a conductive line and a conductive via, and structures formed thereby. In some embodiments, an interconnect opening is formed through one or more dielectric layers over a semiconductor substrate. The interconnect opening has a via opening and a trench over the via opening. A conductive via is formed in the via opening. A nucleation enhancement treatment is performed on one or more exposed dielectric surfaces of the trench. A conductive line is formed in the trench on the one or more exposed dielectric surfaces of the trench and on the conductive via.
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公开(公告)号:US10269649B2
公开(公告)日:2019-04-23
申请号:US15938225
申请日:2018-03-28
发明人: Sung-Li Wang , Neng-Kuo Chen , Ding-Kang Shih , Meng-Chun Chang , Yi-An Lin , Gin-Chen Huang , Chen-Feng Hsu , Hau-Yu Lin , Chih-Hsin Ko , Sey-Ping Sun , Clement Hsingjen Wann
IPC分类号: H01L29/00 , H01L21/8234 , H01L29/78 , H01L29/66 , H01L21/8238 , H01L29/165 , H01L29/161 , H01L29/16 , H01L29/06 , H01L29/417 , H01L27/088 , H01L29/423 , H01L29/51
摘要: A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.
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公开(公告)号:US10049938B2
公开(公告)日:2018-08-14
申请号:US14599246
申请日:2015-01-16
发明人: Sung-Li Wang , Chih-Sheng Chang , Sey-Ping Sun
IPC分类号: H01L29/06 , H01L29/78 , H01L21/8234 , H01L29/66 , H01L21/8238 , H01L29/165 , H01L29/161 , H01L29/16 , H01L29/417 , H01L27/088 , H01L29/51 , H01L29/423
摘要: Semiconductor devices, fin field effect transistor (FinFET) devices, and methods of manufacturing semiconductor devices are disclosed. In some embodiments, a semiconductor device includes a substrate comprising a first fin and a second fin. A first epitaxial fin is disposed over the first fin, and a second epitaxial fin is disposed over the second fin. The second fin is proximate the first fin. The first epitaxial fin and the second epitaxial fin have an upper portion with a substantially pillar shape.
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公开(公告)号:US20170170061A1
公开(公告)日:2017-06-15
申请号:US15444060
申请日:2017-02-27
IPC分类号: H01L21/768 , H01L29/78 , H01L29/66
CPC分类号: H01L21/76856 , H01L21/02532 , H01L21/02579 , H01L21/0262 , H01L21/02639 , H01L21/285 , H01L21/76802 , H01L21/76831 , H01L21/76843 , H01L21/76888 , H01L23/485 , H01L29/0684 , H01L29/41783 , H01L29/41791 , H01L29/66636 , H01L29/66795 , H01L29/7848 , H01L29/7851 , H01L2029/7858 , H01L2924/0002 , H01L2924/00
摘要: A contact structure of a semiconductor device is provided. The contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate, and wherein a surface of the strained material has received a passivation treatment; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a dielectric layer coating the sidewalls and bottom of the opening, wherein the dielectric layer has a thickness ranging from 1 nm to 10 nm; a metal barrier coating an opening of the dielectric layer; and a metal layer filling a coated opening of the dielectric layer.
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