公开(公告)号：US20210083119A1

公开(公告)日：2021-03-18

申请号：US16572812

申请日：2019-09-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Mrunal A. Khaderbad ,  Keng-Chu Lin ,  Sung-Li Wang

IPC分类号： H01L29/78 ,  H01L21/768 ,  H01L29/417 ,  H01L29/66

摘要： A structure includes a transistor including a first source/drain region, a source/drain contact plug over and electrically coupling to the first source/drain region, and a via over and contacting the source/drain contact plug. The via has a bottom portion having a first length, and an upper portion having a second length. The first length is greater than the second length. Both of the first length and the second length are measured in a same direction parallel to a top surface of the source/drain contact plug.

公开(公告)号：US09349726B2

公开(公告)日：2016-05-24

申请号：US14226616

申请日：2014-03-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Ching Lee ,  Hsueh Wen Tsau ,  Mrunal A. Khaderbad ,  Da-Yuan Lee

IPC分类号： H01L27/088 ,  H01L21/28 ,  H01L21/8234

CPC分类号： H01L27/088 ,  H01L21/28008 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/82345 ,  H01L29/66545

摘要： A semiconductor device, and a method of fabrication, is introduced. In an embodiment, a dummy gate stack is formed on a substrate. Lightly-doped source/drain regions and highly-doped source/drain regions are formed in the substrate on either sides of the dummy gate stack. An inter-layer dielectric (ILD) layer is formed over the substrate. Subsequently, the dummy gate stack is removed and a gate stack is formed in an opening in the ILD layer. The gate stack is formed by forming an interfacial layer in the opening of the ILD layer, forming a gate dielectric layer over the interfacial layer, forming a work function metal layer over the gate dielectric layer, and forming one or more gate electrode layers over the work function metal layer. Contacts are formed in the ILD layer and one or more metallization layers are formed over the ILD layer.

摘要翻译： 引入半导体器件和制造方法。 在一个实施例中，在基板上形成虚拟栅极堆叠。 在伪栅极叠层的任一侧上的衬底中形成轻掺杂源极/漏极区域和高掺杂源极/漏极区域。 在衬底上形成层间介电层（ILD）层。 随后，去除虚拟栅极堆叠并且在ILD层的开口中形成栅极堆叠。 通过在ILD层的开口中形成界面层形成栅极叠层，在界面层上形成栅介电层，在栅介电层上形成功函数金属层，并在栅极电介质层的上方形成一个或多个栅电极层 功能金属层。 触点形成在ILD层中，并且在ILD层上形成一个或多个金属化层。

公开(公告)号：US20150279837A1

公开(公告)日：2015-10-01

申请号：US14226616

申请日：2014-03-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Ching Lee ,  Hsueh Wen Tsau ,  Mrunal A. Khaderbad ,  Da-Yuan Lee

IPC分类号： H01L27/088 ,  H01L21/28

CPC分类号： H01L27/088 ,  H01L21/28008 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/82345 ,  H01L29/66545

摘要： A semiconductor device, and a method of fabrication, is introduced. In an embodiment, a dummy gate stack is formed on a substrate. Lightly-doped source/drain regions and highly-doped source/drain regions are formed in the substrate on either sides of the dummy gate stack. An inter-layer dielectric (ILD) layer is formed over the substrate. Subsequently, the dummy gate stack is removed and a gate stack is formed in an opening in the ILD layer. The gate stack is formed by forming an interfacial layer in the opening of the ILD layer, forming a gate dielectric layer over the interfacial layer, forming a work function metal layer over the gate dielectric layer, and forming one or more gate electrode layers over the work function metal layer. Contacts are formed in the ILD layer and one or more metallization layers are formed over the ILD layer.

摘要翻译： 引入半导体器件和制造方法。 在一个实施例中，在基板上形成虚拟栅极堆叠。 在伪栅极叠层的任一侧上的衬底中形成轻掺杂源极/漏极区域和高掺杂源极/漏极区域。 在衬底上形成层间介电层（ILD）层。 随后，去除虚拟栅极堆叠并且在ILD层的开口中形成栅极堆叠。 通过在ILD层的开口中形成界面层形成栅极叠层，在界面层上形成栅介电层，在栅介电层上形成功函数金属层，并在栅极电介质层的上方形成一个或多个栅电极层 功能金属层。 触点形成在ILD层中，并且在ILD层上形成一个或多个金属化层。