A semiconductor device, and a method of fabrication, is introduced. In an embodiment, a dummy gate stack is formed on a substrate. Lightly-doped source/drain regions and highly-doped source/drain regions are formed in the substrate on either sides of the dummy gate stack. An inter-layer dielectric (ILD) layer is formed over the substrate. Subsequently, the dummy gate stack is removed and a gate stack is formed in an opening in the ILD layer. The gate stack is formed by forming an interfacial layer in the opening of the ILD layer, forming a gate dielectric layer over the interfacial layer, forming a work function metal layer over the gate dielectric layer, and forming one or more gate electrode layers over the work function metal layer. Contacts are formed in the ILD layer and one or more metallization layers are formed over the ILD layer.