公开(公告)号：US20240405023A1

公开(公告)日：2024-12-05

申请号：US18326241

申请日：2023-05-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shuen-Shin LIANG ,  Hong-Mao Lee ,  Sung-Li Wang ,  Yan-Ming Tsai ,  Po-Chin Chang ,  Wei-Yip Loh ,  Harry CHIEN ,  Pei-Hua Lee

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/40 ,  H01L29/45 ,  H01L29/66

Abstract: A semiconductor device includes a semiconductor fin protruding from a substrate. The semiconductor device includes a P-type device over the semiconductor fin and an N-type device over the semiconductor fin. The P-type device includes a first source/drain (S/D) feature adjacent a first gate structure. The P-type device includes a dipole layer over the first S/D feature, where the dipole layer includes a first metal and a second metal different from the first metal. The P-type device further includes a first silicide layer over the dipole layer, where the first silicide layer includes the first metal. The N-type device includes a second S/D feature adjacent a second gate structure. The N-type device further includes a second silicide layer directly contacting the second S/D feature, where the second silicide layer includes the first metal, and where a composition of the second silicide layer is different from that of the dipole layer.

公开(公告)号：US20240355742A1

公开(公告)日：2024-10-24

申请号：US18760471

申请日：2024-07-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Cheng-Wei Chang ,  Chien-Shun Liao ,  Sung-Li Wang ,  Shuen-Shin Liang ,  Shu-Lan Chang ,  Yi-Ying Liu ,  Chia-Hung Chu ,  Hsu-Kai Chang

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/53266 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76883 ,  H01L23/5283 ,  H01L23/53238

Abstract: The present disclosure describes a method for the fabrication of ruthenium conductive structures over cobalt conductive structures. In some embodiments, the method includes forming a first opening in a dielectric layer to expose a first cobalt contact and filling the first opening with ruthenium metal to form a ruthenium contact on the first cobalt contact. The method also includes forming a second opening in the dielectric layer to expose a second cobalt contact and a gate structure and filling the second opening with tungsten to form a tungsten contact on the second cobalt contact and the gate structure. Further, the method includes forming a copper conductive structure on the ruthenium contact and the tungsten contact, where the copper from the copper conductive structure is in contact with the ruthenium metal from the ruthenium contact.

公开(公告)号：US11894438B2

公开(公告)日：2024-02-06

申请号：US17353460

申请日：2021-06-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yee-Chia Yeo ,  Sung-Li Wang ,  Chi On Chui ,  Jyh-Cherng Sheu ,  Hung-Li Chiang ,  I-Sheng Chen

IPC: H01L29/45 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/8234 ,  H01L23/522 ,  H01L27/088 ,  H01L29/08 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/45 ,  H01L21/823425 ,  H01L21/823814 ,  H01L21/823821 ,  H01L23/5226 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/7851 ,  H01L21/823807 ,  H01L29/456 ,  H01L2029/7858

Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a first channel, a first source and a first drain; a second channel, a second source and a second drain; and a gate structure disposed over the first and second channels. The gate structure includes a gate dielectric layer and a gate electrode layer. The first source includes a first crystal semiconductor layer and the second source includes a second crystal semiconductor layer. The first source and the second source are connected by an alloy layer made of one or more Group IV element and one or more transition metal elements. The first crystal semiconductor layer is not in direct contact with the second crystal semiconductor layer.

公开(公告)号：US11031300B2

公开(公告)日：2021-06-08

申请号：US16251841

申请日：2019-01-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Sung-Li Wang ,  Peng-Wei Chu ,  Yasutoshi Okuno

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L21/324 ,  H01L29/08 ,  H01L21/02 ,  H01L29/78

Abstract: A method for manufacturing a semiconductor structure is provided. The method includes: receiving a substrate having a first epitaxy region in a first transistor of a first conductive type and a second epitaxy region in a second transistor of a second conductive type; introducing an agent onto the first epitaxy region and the second epitaxy region, wherein the agent is selectively deposited to the second epitaxy region; selectively depositing a first metal layer on the first epitaxy region; and depositing a second metal layer on the first epitaxy region and the second epitaxy region. A semiconductor structure according to the method is also provided.

公开(公告)号：US20210083119A1

公开(公告)日：2021-03-18

申请号：US16572812

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Mrunal A. Khaderbad ,  Keng-Chu Lin ,  Sung-Li Wang

IPC: H01L29/78 ,  H01L21/768 ,  H01L29/417 ,  H01L29/66

Abstract: A structure includes a transistor including a first source/drain region, a source/drain contact plug over and electrically coupling to the first source/drain region, and a via over and contacting the source/drain contact plug. The via has a bottom portion having a first length, and an upper portion having a second length. The first length is greater than the second length. Both of the first length and the second length are measured in a same direction parallel to a top surface of the source/drain contact plug.

公开(公告)号：US20200258746A1

公开(公告)日：2020-08-13

申请号：US16859125

申请日：2020-04-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sung-Li Wang ,  Jyh-Cherng Sheu ,  Huang-Yi Huang ,  Chih-Wei Chang ,  Chi On Chui

IPC: H01L21/285 ,  H01L21/321 ,  H01L29/417 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/535 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

Abstract: A method includes forming a source/drain region, and in a vacuum chamber or a vacuum cluster system, preforming a selective deposition to form a metal silicide layer on the source/drain region, and a metal layer on dielectric regions adjacent to the source/drain region. The method further includes selectively etching the metal layer in the vacuum chamber, and selectively forming a metal nitride layer on the metal silicide layer. The selectively forming the metal nitride layer is performed in the vacuum chamber or a vacuum cluster system without vacuum break.

公开(公告)号：US20200006224A1

公开(公告)日：2020-01-02

申请号：US16569912

申请日：2019-09-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sung-Li Wang ,  Yasutoshi Okuno

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768

Abstract: Embodiments described herein relate generally to one or more methods for forming an interconnect structure, such as a dual damascene interconnect structure comprising a conductive line and a conductive via, and structures formed thereby. In some embodiments, an interconnect opening is formed through one or more dielectric layers over a semiconductor substrate. The interconnect opening has a via opening and a trench over the via opening. A conductive via is formed in the via opening. A nucleation enhancement treatment is performed on one or more exposed dielectric surfaces of the trench. A conductive line is formed in the trench on the one or more exposed dielectric surfaces of the trench and on the conductive via.

公开(公告)号：US20190214296A1

公开(公告)日：2019-07-11

申请号：US16354362

申请日：2019-03-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sung-Li Wang ,  Shuen-Shin Liang ,  Jung-Hao Chang ,  Chia-Hung Chu ,  Keng-Chu Lin

IPC: H01L21/768

CPC classification number: H01L21/76814 ,  H01L21/76847 ,  H01L21/76879 ,  H01L21/76883

Abstract: Embodiments described herein relate generally to one or more methods for forming an interconnect structure, such as a dual damascene interconnect structure comprising a conductive line and a conductive via, and structures formed thereby. In some embodiments, an interconnect opening is formed through one or more dielectric layers over a semiconductor substrate. The interconnect opening has a via opening and a trench over the via opening. A conductive via is formed in the via opening. A nucleation enhancement treatment is performed on one or more exposed dielectric surfaces of the trench. A conductive line is formed in the trench on the one or more exposed dielectric surfaces of the trench and on the conductive via.

公开(公告)号：US10269649B2

公开(公告)日：2019-04-23

申请号：US15938225

申请日：2018-03-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sung-Li Wang ,  Neng-Kuo Chen ,  Ding-Kang Shih ,  Meng-Chun Chang ,  Yi-An Lin ,  Gin-Chen Huang ,  Chen-Feng Hsu ,  Hau-Yu Lin ,  Chih-Hsin Ko ,  Sey-Ping Sun ,  Clement Hsingjen Wann

IPC: H01L29/00 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/161 ,  H01L29/16 ,  H01L29/06 ,  H01L29/417 ,  H01L27/088 ,  H01L29/423 ,  H01L29/51

Abstract: A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.

公开(公告)号：US10049938B2

公开(公告)日：2018-08-14

申请号：US14599246

申请日：2015-01-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sung-Li Wang ,  Chih-Sheng Chang ,  Sey-Ping Sun

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/161 ,  H01L29/16 ,  H01L29/417 ,  H01L27/088 ,  H01L29/51 ,  H01L29/423

Abstract: Semiconductor devices, fin field effect transistor (FinFET) devices, and methods of manufacturing semiconductor devices are disclosed. In some embodiments, a semiconductor device includes a substrate comprising a first fin and a second fin. A first epitaxial fin is disposed over the first fin, and a second epitaxial fin is disposed over the second fin. The second fin is proximate the first fin. The first epitaxial fin and the second epitaxial fin have an upper portion with a substantially pillar shape.