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公开(公告)号：US20220320281A1
公开(公告)日：2022-10-06
申请号：US17217186
申请日：2021-03-30
IPC分类号： H01L29/06 , H01L29/78 , H01L27/092 , H01L29/66
摘要： A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first nanostructure over the substrate. The first nanostructure has a first channel direction, and the first channel direction is [1 0 0], [−1 0 0], [0 1 0], or [0 −1 0]. The semiconductor device structure includes a gate stack over the substrate and surrounding the first nanostructure. The semiconductor device structure includes a first source/drain structure and a second source/drain structure over the substrate and over opposite sides of the gate stack.
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公开(公告)号：US20240097011A1
公开(公告)日：2024-03-21
申请号：US18526360
申请日：2023-12-01
发明人： Han-Yu LIN , Fang-Wei LEE , Kai-Tak LAM , Raghunath PUTIKAM , Tzer-Min SHEN , Li-Te LIN , Pinyen LIN , Cheng-Tzu YANG , Tzu-Li LEE , Tze-Chung LIN
IPC分类号： H01L29/66 , H01L21/8234 , H01L29/78
CPC分类号： H01L29/6681 , H01L21/823431 , H01L29/785 , H01L2029/7858
摘要： A method includes forming a fin structure over a substrate, wherein the fin structure comprises first semiconductor layers and second semiconductor layers alternately stacked over a substrate; forming a dummy gate structure over the fin structure; removing a portion of the fin structure uncovered by the dummy gate structure; performing a selective etching process to laterally recess the first semiconductor layers, including injecting a hydrogen-containing gas from a first gas source of a processing tool to the first semiconductor layers and the second semiconductor layers; and injecting an F2 gas from a second gas source of the processing tool to the first semiconductor layers and the second semiconductor layers; forming inner spacers on opposite end surfaces of the laterally recessed first semiconductor layers of the fin structure; and replacing the dummy gate structure and the first semiconductor layers with a metal gate structure.
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3.发明公开公开(公告)号：US20240021709A1
公开(公告)日：2024-01-18
申请号：US17865846
申请日：2022-07-15
发明人： Chansyun David YANG , Huang-Lin CHAO , Hsiang-Pi CHANG , Yen-Tien TUNG , Chung-Liang CHENG , Yu-Chia LIANG , Shen-Yang LEE , Yao-Sheng HUANG , Tzer-Min SHEN , Pinyen LIN
IPC分类号： H01L29/66 , H01L21/8238 , H01L21/768 , H01L21/28
CPC分类号： H01L29/66795 , H01L21/823807 , H01L21/76811 , H01L21/28185
摘要： A semiconductor device includes a channel layer, an interfacial layer, a gate dielectric layer, a gate electrode, dipole elements, and additional elements. The interfacial layer is disposed on the channel layer, and includes an insulating material. The gate dielectric layer is disposed over the interfacial layer such that the channel layer is separated from the gate dielectric layer by the interfacial layer. The gate electrode is disposed on the gate dielectric layer. The dipole elements are present in at least one of the interfacial layer and the gate dielectric layer in a predetermined amount such that the semiconductor device has a predetermined threshold voltage. The additional elements are located at a region where the dipole elements are present so as to reduce interfacial defects caused by the dipole elements. The additional elements are different from the dipole elements. Methods for manufacturing the semiconductor device are also disclosed.
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公开(公告)号：US20240233795A1
公开(公告)日：2024-07-11
申请号：US18615398
申请日：2024-03-25
发明人： Huan-Sheng WEI , Tzer-Min SHEN , Zhiqiang WU
CPC分类号： G11C11/2275 , G11C11/223 , G11C11/2273 , H10B51/30 , H10B51/40
摘要： A memory circuit includes a plurality of memory cells, each memory cell of the plurality of memory cells including a gate electrode, a ferroelectric layer adjacent to the gate electrode, a channel layer adjacent to the ferroelectric layer, the channel layer including indium gallium zinc oxide (IGZO), and source and drain contacts adjacent to the channel layer opposite the ferroelectric layer. The memory circuit is configured to, during write operations to a memory cell of the plurality of memory cells, apply a plurality of voltage levels to the gate electrode relative to a ground voltage level applied to the source and drain contacts, a first voltage level of the plurality of voltage levels has a positive polarity and a first magnitude, and a second voltage level of the plurality of voltage levels has a negative polarity and a second magnitude greater than the first magnitude.
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公开(公告)号：US20240063263A1
公开(公告)日：2024-02-22
申请号：US18500225
申请日：2023-11-02
IPC分类号： H01L29/06 , H01L27/092 , H01L29/66 , H01L29/78
CPC分类号： H01L29/0673 , H01L27/0924 , H01L29/66795 , H01L29/7851
摘要： A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first nanostructure over the substrate. The first nanostructure has a (001) surface, the first nanostructure has a first channel direction on the (001) surface, and the first channel direction is [0 1 0] or [0 −1 0]. The semiconductor device structure includes a gate stack surrounding the first nanostructure. The semiconductor device structure includes a first source/drain structure and a second source/drain structure over the substrate and over opposite sides of the gate stack. The first nanostructure is between the first source/drain structure and the second source/drain structure, and the first channel direction is from the first source/drain structure to the second source/drain structure.
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公开(公告)号：US20220173224A1
公开(公告)日：2022-06-02
申请号：US17152432
申请日：2021-01-19
发明人： Han-Yu LIN , Fang-Wei LEE , Kai-Tak LAM , Raghunath PUTIKAM , Tzer-Min SHEN , Li-Te LIN , Pinyen LIN , Cheng-Tzu YANG , Tzu-Li LEE , Tze-Chung LIN
IPC分类号： H01L29/66 , H01L29/78 , H01L21/8234
摘要： A method includes forming a fin structure including a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked over a substrate. A dummy gate structure is formed across the fin structure. The exposed second portions of the fin structure are removed. A selective etching process is performed, using a gas mixture including a hydrogen-containing gas and a fluorine-containing gas, to laterally recess the first semiconductor layers. Inner spacers are formed on opposite end surfaces of the laterally recessed first semiconductor layers. Source/drain epitaxial structures are formed on opposite end surfaces of the second semiconductor layers. The dummy gate structure is removed to expose the first portion of the fin structure. The laterally recessed first semiconductor layers are removed. A gate structure is formed to surround each of the second semiconductor layers.
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公开(公告)号：US20240332393A1
公开(公告)日：2024-10-03
申请号：US18741963
申请日：2024-06-13
发明人： Hsu-Kai CHANG , Jhih-Rong HUANG , Yen-Tien TUNG , Chia-Hung CHU , Shuen-Shin LIANG , Tzer-Min SHEN , Pinyen LIN , Sung-Li WANG
IPC分类号： H01L29/45 , H01L21/285 , H01L21/8238 , H01L27/092 , H01L29/08 , H01L29/417 , H01L29/66 , H01L29/78
CPC分类号： H01L29/45 , H01L21/28518 , H01L21/823814 , H01L21/823821 , H01L21/823871 , H01L27/0924 , H01L29/0847 , H01L29/41791 , H01L29/66795 , H01L29/7851
摘要： A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second gate structures disposed on first and second fin structures, first and second source/drain (S/D) regions disposed on the first and second fin structures, first and second contact structures disposed on the first and second S/D regions, and a dipole layer disposed at an interface between the first nWFM silicide layer and the first S/D region. The first contact structure includes a first nWFM silicide layer disposed on the first S/D region and a first contact plug disposed on the first nWFM silicide layer. The second contact structure includes a pWFM silicide layer disposed on the second S/D region, a second nWFM silicide layer disposed on the pWFM silicide layer, and a second contact plug disposed on the pWFM silicide layer.
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公开(公告)号：US20230083548A1
公开(公告)日：2023-03-16
申请号：US18056807
申请日：2022-11-18
发明人： Huan-Sheng WEI , Tzer-Min SHEN , Zhiqiang WU
IPC分类号： G11C11/22 , H01L27/11592 , H01L27/1159
摘要： A memory circuit includes a memory array including a plurality of memory cells, each memory cell of the plurality of memory cells including an n-type channel layer including a metal oxide material, and a gate structure overlying and adjacent to the n-type channel layer, the gate structure including a conductive layer overlying a ferroelectric layer. The memory circuit is configured to apply a gate voltage to each memory cell of the plurality of memory cells in first and second write operations, the gate voltage has a positive polarity and a first magnitude in the first write operation and a negative polarity and a second magnitude greater than the first magnitude in the second write operation.
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公开(公告)号：US20210375345A1
公开(公告)日：2021-12-02
申请号：US17198790
申请日：2021-03-11
发明人： Huan-Sheng WEI , Tzer-Min SHEN , Zhiqiang WU
IPC分类号： G11C11/22 , H01L27/1159 , H01L27/11592
摘要： A memory circuit includes a memory array including a plurality of memory cells, each memory cell including a gate structure including a ferroelectric layer and a channel layer adjacent to the gate structure, the channel layer including a metal oxide material. A driver circuit is configured to output a gate voltage to the gate structure of a memory cell, the gate voltage having a positive polarity and a first magnitude in in a first write operation and a negative polarity and a second magnitude in in a second write operation, and to control the second magnitude to be greater than the first magnitude.
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