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公开(公告)号：US20240332020A1
公开(公告)日：2024-10-03
申请号：US18740970
申请日：2024-06-12
发明人： Sheng-Lin HSIEH , I-Chih CHEN , Ching-Pei HSIEH , Kuan Jung CHEN
IPC分类号： H01L21/027 , H01L21/033 , H01L21/768
CPC分类号： H01L21/0276 , H01L21/0332 , H01L21/0337 , H01L21/76816 , H01L21/76819
摘要： A method of forming a semiconductor device structure includes forming a first resist structure over a hard mask. The method further includes patterning the first resist structure to form a trench therein. The method further includes performing a first hydrogen plasma treatment to the patterned first resist structure, wherein the first hydrogen plasma treatment is configured to smooth sidewalls of the trench. The method further includes patterning the hard mask using the patterned resist structure as an etch mask. The method further includes forming a second resist structure over the patterned hard mask. The method further includes patterning the second resist structure to form an opening therein. The method further includes performing a second hydrogen plasma treatment to the patterned second resist structure. The method further includes patterning the patterned hard mask using the patterned second resist structure as a second etch mask.
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公开(公告)号：US20240071470A1
公开(公告)日：2024-02-29
申请号：US18499449
申请日：2023-11-01
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. , TSMC Nanjing Company Limited , TSMC China Company Limited
发明人： He-Zhou WAN , Xiu-Li YANG , Mu-Yang YE , Yan-Bo SONG
IPC分类号： G11C11/408 , G11C5/06 , G11C11/4074 , G11C11/4094
CPC分类号： G11C11/4085 , G11C5/063 , G11C11/4074 , G11C11/4087 , G11C11/4094
摘要： A memory device includes a first transistor, a second transistor and a third transistor. The first transistor is coupled to a first word line at a first node. The second transistor is coupled to a second word line different from the first word line at a second node. A control terminal of the first transistor is coupled to a control terminal of the second transistor. The third transistor is coupled between a ground and a third node which is coupled to each of the first node and the second node. In a layout view, each of the first transistor and the second transistor has a first length along a direction. The first transistor, the third transistor and second transistor are arranged in order along the direction. A method is also disclosed herein.
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公开(公告)号：US20240030921A1
公开(公告)日：2024-01-25
申请号：US18482172
申请日：2023-10-06
发明人： Ying HUANG , Changlin HUANG , Jing DING , Qingchao MENG
IPC分类号： H03K19/0185 , G06F30/392
CPC分类号： H03K19/018521 , G06F30/392 , G06F2119/06
摘要： A method of generating an integrated circuit (IC) layout diagram includes arranging a first portion of first through fourth pluralities of active regions and a plurality of gate regions of a cell as a functional circuit in a first portion of the cell, arranging a second portion of the first through fourth pluralities of active regions and the plurality of gate regions of the cell as a one of a decoupling capacitor or an antenna diode in a second portion of the cell, and storing an IC layout diagram of the cell in a storage device.
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公开(公告)号：US20240030920A1
公开(公告)日：2024-01-25
申请号：US18479378
申请日：2023-10-02
发明人： Jing DING , Zhang-Ying YAN , Qingchao MENG , Yi-Ting CHEN
IPC分类号： H03K19/0185 , H03K3/356
CPC分类号： H03K19/018521 , H03K3/356182 , H03K3/356113
摘要： A semiconductor device includes: first and second input circuits in a central region and correspondingly configured to operate in a first voltage domain; first and second single bit level shifters (SBLSs) correspondingly in first and second regions at first and second sides of the central region relative to a first direction and electrically coupled correspondingly to the first and second input circuits, and correspondingly configured to operate in a second voltage domain; and a control circuit configured to toggle each of the first and second SBLSs between a normal state and a standby state when a control signal is received from the control circuit.
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公开(公告)号：US20240017190A1
公开(公告)日：2024-01-18
申请号：US18447174
申请日：2023-08-09
发明人： Chian-Niang LIN , Barry TSAO , Tsung Tso TSAI
CPC分类号： B01D19/0042 , G03F7/70858 , B01D19/0021
摘要： A method includes receiving, in a first vessel, a flow of fluid from a second vessel, wherein the flow of fluid is generated by pressurizing a head space over the fluid in the second vessel; capturing the flow of fluid from the second vessel at an upper end of a de-bubbling slide in the first vessel; and directing the flow of fluid along a flow surface of de-bubbling slide to a lower portion of the first vessel, such that bubbles and dissolved gases in the fluid exit the fluid on the flow surface of the de-bubbling slide.
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公开(公告)号：US11876088B2
公开(公告)日：2024-01-16
申请号：US17527883
申请日：2021-11-16
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. , TSMC CHINA COMPANY, LIMITED , TSMC NANJING COMPANY, LIMITED
发明人： Yang Zhou , Liu Han , Qingchao Meng , XinYong Wang , ZeJian Cai
IPC分类号： H01L27/02 , H01L27/092 , H01L25/065 , H01L23/48 , H01L21/265 , H01L21/768 , H01L21/8238 , H01L25/00 , G06F30/392 , H01L21/74
CPC分类号： H01L27/0207 , G06F30/392 , H01L21/26513 , H01L21/74 , H01L21/76898 , H01L21/823892 , H01L23/481 , H01L25/0657 , H01L25/50 , H01L27/0928 , H01L2225/06513 , H01L2225/06541
摘要： An integrated circuit (IC) structure includes a continuous well including first through third well portions. The continuous well is one of an n-well or a p-well, the first well portion extends in a first direction, the second well portion extends from the first well portion in a second direction perpendicular to the first direction, and the third well portion extends from the first well portion in the second direction parallel to the second well portion.
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公开(公告)号：US11855192B2
公开(公告)日：2023-12-26
申请号：US17152432
申请日：2021-01-19
发明人： Han-Yu Lin , Fang-Wei Lee , Kai-Tak Lam , Raghunath Putikam , Tzer-Min Shen , Li-Te Lin , Pinyen Lin , Cheng-Tzu Yang , Tzu-Li Lee , Tze-Chung Lin
IPC分类号： H01L29/66 , H01L21/8234 , H01L29/78
CPC分类号： H01L29/6681 , H01L21/823431 , H01L29/785 , H01L2029/7858
摘要： A method includes forming a fin structure including a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked over a substrate. A dummy gate structure is formed across the fin structure. The exposed second portions of the fin structure are removed. A selective etching process is performed, using a gas mixture including a hydrogen-containing gas and a fluorine-containing gas, to laterally recess the first semiconductor layers. Inner spacers are formed on opposite end surfaces of the laterally recessed first semiconductor layers. Source/drain epitaxial structures are formed on opposite end surfaces of the second semiconductor layers. The dummy gate structure is removed to expose the first portion of the fin structure. The laterally recessed first semiconductor layers are removed. A gate structure is formed to surround each of the second semiconductor layers.
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公开(公告)号：US11854943B2
公开(公告)日：2023-12-26
申请号：US18153475
申请日：2023-01-12
发明人： Hidehiro Fujiwara , Tze-Chiang Huang , Hong-Chen Cheng , Yen-Huei Chen , Hung-Jen Liao , Jonathan Tsung-Yung Chang , Yun-Han Lee , Lee-Chung Lu
IPC分类号： G11C16/04 , H01L23/48 , H10B10/00 , G11C11/418 , H01L21/768
CPC分类号： H01L23/481 , G11C11/418 , H01L21/76898 , H10B10/18
摘要： An integrated circuit (IC) package includes a logic die, a substrate, a memory die positioned between the logic die and the substrate, and a power distribution structure configured to electrically couple the logic die to the substrate. The power distribution structure includes a plurality of conductive segments positioned between the logic die and the memory die, a plurality of bump structures positioned between the memory die and the substrate, and a plurality of through-silicon vias (TSVs) electrically coupled to the plurality of conductive segments and the plurality of bump structures, and a TSV of the plurality of TSVs extends through, and is electrically isolated from, a memory macro of the memory die.
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公开(公告)号：US20230402446A1
公开(公告)日：2023-12-14
申请号：US18447857
申请日：2023-08-10
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. , TSMC NANJING COMPANY, LIMITED , TSMC CHINA COMPANY, LIMITED
发明人： Liu HAN , Xin Yong WANG , Qingchao MENG , Huaixin XIAN , Jing DING
CPC分类号： H01L27/0207 , H03K19/0016 , H01L27/0629
摘要： A semiconductor device having a cell region, the cell region including a first set of one or more first blocks and a second set of one or more second blocks. Each of the first blocks including a clock gate and each of the second blocks includes a decoupling capacitor. The first set has two or more first blocks and/or the second set has two or more second blocks. The first blocks of the first set are interleaved with the second blocks of the second set.
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公开(公告)号：US11769669B2
公开(公告)日：2023-09-26
申请号：US17165078
申请日：2021-02-02
发明人： Min Han Hsu , Jung-Chih Tsao
CPC分类号： H01L21/28088 , H01L29/4966 , H01L29/66545 , H01L29/66795 , H01L29/7851
摘要： The semiconductor device includes a semiconductor fin, and a gate stack over the semiconductor fin. The gate stack includes a gate dielectric layer over a channel region of the semiconductor fin, a work function material layer over the gate dielectric layer, wherein the work function material layer includes dopants, and a gate electrode layer over the work function material layer. The gate dielectric layer is free of the dopants.
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