公开(公告)号：US20240341074A1

公开(公告)日：2024-10-10

申请号：US18749271

申请日：2024-06-20

申请人： Socionext Inc.

发明人： Masanobu HIROSE ,  Yasunori MURASE

IPC分类号： H10B10/00 ,  G11C11/412 ,  G11C11/419

CPC分类号： H10B10/12 ,  G11C11/412 ,  G11C11/419 ,  H10B10/18

摘要： Nanosheets 21 to 23 are formed in line in this order in the X direction, and nanosheets 24 to 26 are formed in line in this order in the X direction. In a buried interconnect layer, a power line 11 is formed between the nanosheets 22 and 25 as viewed in plan. A face of the nanosheet 22 on a first side as one of the sides in the X direction is exposed from a gate interconnect 32. A face of the nanosheet 25 on a second side as the other side in the X direction is exposed from a gate interconnect 35.

公开(公告)号：US12114473B2

公开(公告)日：2024-10-08

申请号：US17828123

申请日：2022-05-31

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jhon-Jhy Liaw

IPC分类号： G11C7/12 ,  G11C11/412 ,  G11C11/413 ,  G11C11/419 ,  H10B10/00 ,  G11C8/08 ,  G11C8/16

CPC分类号： H10B10/18 ,  G11C11/412 ,  G11C11/413 ,  G11C11/419 ,  G11C7/12 ,  G11C8/08 ,  G11C8/16

摘要： Semiconductor devices are provided. A write port circuit is configured to perform a write function according to the write word line and the first and second write bit lines. The first read port circuit is configured to perform first read function according to the first read bit line and the first read word line. The second read port circuit is configured to perform second read function according to the second read bit line and the second read word line. The transistors of the first and second read port circuits share a first active structure extending in the first direction. The first read bit line and the second read bit line extend in the first direction in a first metallization layer, and the first write bit line and the second write bit line extend in the first direction in a second metallization layer over the first metallization layer.

公开(公告)号：US20240306361A1

公开(公告)日：2024-09-12

申请号：US18349298

申请日：2023-07-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ping-Wei Wang ,  Lien-Jung Hung ,  Jui-Lin Chen

IPC分类号： H10B10/00

CPC分类号： H10B10/18 ,  H10B10/125

摘要： A semiconductor structure includes a memory cell, a logic cell, and a transition region between the memory cell and the logic cell. The memory cell includes a first active region and a plurality of first gate structures with a gate pitch. The logic cell includes a second active region and a plurality of second gate structures with the gate pitch. The transition region includes a first dielectric feature and a second dielectric feature. The first dielectric feature divides the first active region into a first segment partially in the transition region and a second segment fully in the transition region. The second dielectric feature divides the second active region into a third segment partially in the transition region and a fourth segment fully in the transition region.

公开(公告)号：US12089391B2

公开(公告)日：2024-09-10

申请号：US17853098

申请日：2022-06-29

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Jhon-Jhy Liaw

IPC分类号： G11C11/412 ,  G11C7/12 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/4097 ,  H10B10/00

CPC分类号： H10B10/12 ,  G11C7/12 ,  G11C11/4085 ,  G11C11/4096 ,  G11C11/4097 ,  H10B10/18

摘要： Semiconductor devices are provided. A memory cell includes a first pull-down transistor, a second pull-down transistor, a first pass-gate transistor, and a second pass-gate transistor formed over a P-type well region, and a first pull-up transistor, a second pull-up transistor, a first isolation transistor, and a second isolation transistor formed over an N-type well region. The first and second pull-down transistors and the first and second pass-gate transistors share a first active region. The first and second pull-up transistors and the first and second isolation transistors share a second active region. The gates of the first and second isolation transistors are electrically connected to a VDD line. The gates of the first and second pass-gate transistors are electrically connected to a WL landing pad. The sources of the first and second pass-gate transistors are electrically connected to the first bit line and the second bit line, respectively.

公开(公告)号：US20240251539A1

公开(公告)日：2024-07-25

申请号：US18587506

申请日：2024-02-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Feng-Ching Chu ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC分类号： H10B10/00 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3105 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC分类号： H10B10/12 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/31053 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785 ,  H10B10/18

摘要： A semiconductor device according to the present disclosure includes a gate-all-around (GAA) transistor in a first device area and a fin-type field effect transistor (FinFET) in a second device area. The GAA transistor includes a plurality of vertically stacked channel members and a first gate structure over and around the plurality of vertically stacked channel members. The FinFET includes a fin-shaped channel member and a second gate structure over the fin-shaped channel member. The fin-shaped channel member includes semiconductor layers interleaved by sacrificial layers.

公开(公告)号：US20240120258A1

公开(公告)日：2024-04-11

申请号：US18373709

申请日：2023-09-27

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Taehyung KIM ,  Hoyoung Tang ,  Yunsick Park

IPC分类号： H01L23/48 ,  H10B10/00

CPC分类号： H01L23/481 ,  H10B10/125 ,  H10B10/18

摘要： Provided is an integrated circuit including a cell region in which a plurality of cells are arranged, and a peripheral region in which a circuit configured to control the plurality of cells is arranged, wherein the cell region further includes a plurality of first gate lines over a substrate, a plurality of first patterns in a first wiring layer above the plurality of first gate lines, a plurality of second patterns extending in a first horizontal direction in a backside wiring layer under the substrate, and a plurality of first vias, each of the plurality of first vias passing through the substrate in a vertical direction, wherein each of the plurality of first vias includes a top surface connected to a respective one of the plurality of first patterns and a bottom surface connected to a respective one of the plurality of second patterns.

公开(公告)号：US11942558B2

公开(公告)日：2024-03-26

申请号：US17574166

申请日：2022-01-12

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Mongsong Liang ,  Sung-Dae Suk ,  Geumjong Bae

IPC分类号： H01L29/786 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00

CPC分类号： H01L29/78696 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/78618 ,  H10B10/12 ,  H10B10/18

摘要： A semiconductor device includes a first transistor, a second transistor and a third transistor provided on a substrate, the first to third transistors respectively including source and drain regions spaced apart from each other, a gate structure extending in a first direction on the substrate and interposed between the source and drain regions, and a channel region connecting the source and drain regions to each other. A channel region of the second transistor and a channel region of the third transistor respectively include a plurality of channel portions, the plurality of channel portions spaced apart from each other in a second direction, perpendicular to an upper surface of the substrate, and connected to the source and drain regions, respectively. A width of a channel portion of the third transistor in the first direction is greater than a width of a channel portion of the second transistor in the first direction.

公开(公告)号：US11930629B2

公开(公告)日：2024-03-12

申请号：US17546241

申请日：2021-12-09

申请人： Samsung Electronics Co., Ltd.

发明人： Hee Bum Hong ,  Yongrae Cho

IPC分类号： H10B10/00 ,  G11C5/14 ,  G11C11/412

CPC分类号： H10B10/18 ,  G11C5/14 ,  H10B10/12 ,  G11C11/412

摘要： Disclosed is a semiconductor memory device comprising a plurality of memory cells each including an access transistor, a pull-up transistor, and a pull-down transistor on a substrate, a first line layer on the memory cells and including a first lower landing pad and a second lower landing pad, a second line layer on the first line layer and including a ground line having an opening and an upper landing pad in the opening, and a third line layer including a word line on the second line layer. The ground line is electrically connected through the first lower landing pad to a terminal of the pull-down transistor. The word line is electrically connected through the upper landing pad and the second lower landing pad to a terminal of the access transistor.

公开(公告)号：US11856747B2

公开(公告)日：2023-12-26

申请号：US17751426

申请日：2022-05-23

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yangsyu Lin ,  Chi-Lung Lee ,  Chien-Chi Tien ,  Chiting Cheng

IPC分类号： H10B10/00 ,  H01L27/02 ,  H01L27/092 ,  G11C11/419 ,  H01L23/522 ,  G11C11/412 ,  H01L23/528

CPC分类号： H10B10/18 ,  G11C11/412 ,  G11C11/419 ,  H01L23/528 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/0928 ,  H10B10/12

摘要： A static random access memory (SRAM) periphery circuit includes a first n-type transistor and a second n-type transistor that are disposed in a first well region of first conductivity type, the first well region occupies a first distance in a row direction equal to a bitcell-pitch of an SRAM array. The SRAM periphery circuit includes a first p-type transistor and a second p-type transistor that are disposed in a second well region of second conductivity type. The second well region occupies a second distance in the row direction equal to the bitcell-pitch of the SRAM array. The second well region is disposed adjacent to the first well region in the row direction.

公开(公告)号：US11856745B2

公开(公告)日：2023-12-26

申请号：US17860977

申请日：2022-07-08

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Kuan Lin ,  Chang-Ta Yang ,  Ping-Wei Wang ,  Kuo-Yi Chao ,  Mei-Yun Wang

IPC分类号： H10B10/00 ,  G11C11/412 ,  H01L29/66 ,  H01L23/522 ,  H01L27/02 ,  H01L21/768

CPC分类号： H10B10/12 ,  G11C11/412 ,  H01L21/76895 ,  H01L23/5226 ,  H01L27/0207 ,  H01L29/66477 ,  H10B10/18

摘要： An integrated circuit structure in which a gate overlies channel region in an active area of a first transistor. The first transistor includes a channel region, a source region and a drain region. A conductive contact is coupled to the drain region of the first transistor. A second transistor that includes a channel region, a source region a drain region is adjacent to the first transistor. The gate of the second transistor is spaced from the gate of the first transistor. A conductive via passes through an insulation layer to electrically connect to the gate of the second transistor. An expanded conductive via overlays both the conductive contact and the conductive via to electrically connect the drain of the first transistor to the gate of the second transistor.