公开(公告)号：US11968817B2

公开(公告)日：2024-04-23

申请号：US17682061

申请日：2022-02-28

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jui-Lin Chen ,  Chao-Yuan Chang ,  Ping-Wei Wang ,  Fu-Kai Yang ,  Ting Fang ,  I-Wen Wu ,  Shih-Hao Lin

IPC分类号： H10B10/00 ,  H01L21/02 ,  H01L21/768 ,  H01L23/522 ,  H01L29/40 ,  H01L29/417

CPC分类号： H10B10/12 ,  H01L21/02063 ,  H01L21/76816 ,  H01L21/76831 ,  H01L23/5226 ,  H01L29/401 ,  H01L29/41791

摘要： A semiconductor device includes a fin structure. A source/drain region is formed on the fin structure. A first gate structure is disposed over the fin structure. A source/drain contact is disposed over the source/drain region. The source/drain contact has a protruding segment that protrudes at least partially over the first gate structure. The source/drain contact electrically couples together the source/drain region and the first gate structure.

公开(公告)号：US20220352181A1

公开(公告)日：2022-11-03

申请号：US17813782

申请日：2022-07-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Chuan Yang ,  Chia-Hao Pao ,  Yu-Kuan Lin ,  Lien-Jung Hung ,  Ping-Wei Wang ,  Shih-Hao Lin

IPC分类号： H01L27/11 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

摘要： A semiconductor device according to the present disclosure includes a gate extension structure, a first source/drain feature and a second source/drain feature, a vertical stack of channel members extending between the first source/drain feature and the second source/drain feature along a direction, and a gate structure wrapping around each of the vertical stack of channel members. The gate extension structure is in direct contact with the first source/drain feature.

公开(公告)号：US20220037340A1

公开(公告)日：2022-02-03

申请号：US16945146

申请日：2020-07-31

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Chuan Yang ,  Chia-Hao Pao ,  Yu-Kuan Lin ,  Lien Jung Hung ,  Ping-Wei Wang ,  Shih-Hao Lin

IPC分类号： H01L27/11 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

摘要： A semiconductor device according to the present disclosure includes a gate extension structure, a first source/drain feature and a second source/drain feature, a vertical stack of channel members extending between the first source/drain feature and the second source/drain feature along a direction, and a gate structure wrapping around each of the vertical stack of channel members. The gate extension structure is in direct contact with the first source/drain feature.

公开(公告)号：US20210242222A1

公开(公告)日：2021-08-05

申请号：US16781274

申请日：2020-02-04

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsin-Wen Su ,  Lien Jung Hung ,  Ping-Wei Wang ,  Yu-Kuan Lin ,  Shih-Hao Lin

IPC分类号： H01L27/112 ,  G11C17/14

摘要： In some embodiments, the present disclosure relates to a one-time program (OTP) memory cell. The OTP memory cell includes a read transistor and a program transistor neighboring the read transistor. The read transistor includes a read dielectric layer and a read gate electrode overlying the read dielectric layer. The program transistor includes a program dielectric layer and a program gate electrode overlying the program dielectric layer. The program transistor has a smaller breakdown voltage than the read transistor.

公开(公告)号：US10522553B2

公开(公告)日：2019-12-31

申请号：US16047586

申请日：2018-07-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuo-Hsiu Hsu ,  Yu-Kuan Lin ,  Feng-Ming Chang ,  Lien Jung Hung ,  Ping-Wei Wang

IPC分类号： H01L27/11 ,  H01L27/092 ,  G11C11/419 ,  G11C11/412 ,  G11C11/413

摘要： A semiconductor device includes first, second, third, and fourth active regions arranged along a first direction. The first, second, third, and fourth active regions includes channel regions and source/drain (S/D) regions of first, second, third, and fourth transistors respectively, the first and fourth transistors are of a first conductivity type, and the second and third transistors are of a second conductivity type opposite the first conductivity type. The semiconductor device further includes a fifth active region between the second and third active regions. The fifth active region includes channel regions and S/D regions of fifth and sixth transistors that are of same conductivity type. The semiconductor device further includes first, second, third, fourth, fifth, and sixth gates. The first through sixth gates are disposed over the channel regions of the first through sixth transistors respectively. The first, second, and fifth gates are electrically connected.

公开(公告)号：US20240331765A1

公开(公告)日：2024-10-03

申请号：US18741051

申请日：2024-06-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ping-Wei Wang ,  Chia-Hao Pao ,  Choh Fei Yeap ,  Yu-Kuan Lin ,  Kian-Long Lim

IPC分类号： G11C11/412 ,  G11C11/419 ,  H10B10/00

CPC分类号： G11C11/412 ,  G11C11/419 ,  H10B10/12

摘要： Memory devices are provided. In an embodiment, a memory device includes a static random access memory (SRAM) array. The SRAM array includes a static random access memory (SRAM) array. The SRAM array includes a first subarray including a plurality of first SRAM cells and a second subarray including a plurality of second SRAM cells. Each n-type transistor in the plurality of first SRAM cells includes a first work function stack and each n-type transistor in the plurality of second SRAM cells includes a second work function stack different from the first work function stack.

公开(公告)号：US20240292592A1

公开(公告)日：2024-08-29

申请号：US18655833

申请日：2024-05-06

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Chuan Yang ,  Chia-Hao Pao ,  Yu-Kuan Lin ,  Lien-Jung Hung ,  Ping-Wei Wang ,  Shih-Hao Lin

IPC分类号： H10B10/00 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC分类号： H10B10/125 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

摘要： A semiconductor device according to the present disclosure includes a gate extension structure, a first source/drain feature and a second source/drain feature, a vertical stack of channel members extending between the first source/drain feature and the second source/drain feature along a direction, and a gate structure wrapping around each of the vertical stack of channel members. The gate extension structure is in direct contact with the first source/drain feature.

公开(公告)号：US12048135B2

公开(公告)日：2024-07-23

申请号：US18064859

申请日：2022-12-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuo-Hsiu Hsu ,  Feng-Ming Chang ,  Kian-Long Lim ,  Ping-Wei Wang ,  Lien Jung Hung ,  Ruey-Wen Chang

IPC分类号： G11C5/06 ,  G11C7/12 ,  G11C8/08 ,  G11C11/412 ,  G11C11/417 ,  H10B10/00

CPC分类号： H10B10/12 ,  G11C7/12 ,  G11C8/08 ,  G11C11/412 ,  G11C11/417

摘要： A semiconductor structure includes an SRAM cell that includes first and second pull-up (PU) transistors, first and second pull-down (PD) transistors, and first and second pass-gate (PG) transistors. A source, a drain, and a channel of the first PU transistor and a source, a drain, and a channel of the second PU transistor are collinear. A source, a drain, and a channel of the first PD transistor, a source, a drain, and a channel of the second PD transistor, a source, a drain, and a channel of the first PG transistor, and a source, a drain, and a channel of the second PG transistor are collinear.

公开(公告)号：US20240203486A1

公开(公告)日：2024-06-20

申请号：US18418779

申请日：2024-01-22

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Chuan YANG ,  Jui-Wen Chang ,  Feng-Ming Chang ,  Kian-Long Lim ,  Kuo-Hsiu Hsu ,  Lien Jung Hung ,  Ping-Wei Wang

IPC分类号： G11C11/417 ,  H01L29/423 ,  H10B10/00

CPC分类号： G11C11/417 ,  H01L29/42392 ,  H10B10/125

摘要： The present disclosure describes a method for memory cell placement. The method can include placing a memory cell region in a layout area and placing a well pick-up region and a first power supply routing region along a first side of the memory cell region. The method also includes placing a second power supply routing region and a bitline jumper routing region along a second side of the memory cell region, where the second side is on an opposite side to that of the first side. The method further includes placing a device region along the second side of the memory cell region, where the bitline jumper routing region is between the second power supply routing region and the device region.

公开(公告)号：US11956948B2

公开(公告)日：2024-04-09

申请号：US17711448

申请日：2022-04-01

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Hsin-Wen Su ,  Yu-Kuan Lin ,  Shih-Hao Lin ,  Lien-Jung Hung ,  Ping-Wei Wang

IPC分类号： H10B20/20 ,  H01L21/02 ,  H01L21/306 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786 ,  H10B20/00

CPC分类号： H10B20/20 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/30604 ,  H01L21/823431 ,  H01L29/0673 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78696 ,  H10B20/00

摘要： A memory device includes a substrate, a first transistor and a second transistor, a first word line, a second word line, and a bit line. The first transistor and the second transistor are over the substrate and are electrically connected to each other, in which each of the first and second transistors includes first semiconductor layers and second semiconductor layers, a gate structure, and source/drain structures, in which the first semiconductor layers are in contact with the second semiconductor layers, and a width of the first semiconductor layers is narrower than a width of the second semiconductor layers. The first word line is electrically connected to the gate structure of the first transistor. The second word line is electrically connected to the gate structure of the second transistor. The bit line is electrically connected to a first one of the source/drain structures of the first transistor.