公开(公告)号：US12101921B2

公开(公告)日：2024-09-24

申请号：US17871764

申请日：2022-07-22

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shih-Hao Lin ,  Chih-Chuan Yang ,  Hsin-Wen Su ,  Kian-Long Lim ,  Chien-Chih Lin

IPC分类号： H10B10/00 ,  G11C11/412 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/10 ,  H01L29/49 ,  H01L29/66

CPC分类号： H10B10/12 ,  G11C11/412 ,  H01L21/28123 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/4991 ,  H01L29/66545 ,  H01L29/6656

摘要： An N-type metal oxide semiconductor (NMOS) transistor includes a first gate and a first spacer structure disposed on a first sidewall of the first gate in a first direction. The first spacer structure has a first thickness in the first direction and measured from an outermost point of an outer surface of the first spacer structure to the first sidewall. A P-type metal oxide semiconductor (PMOS) transistor includes a second gate and a second spacer structure disposed on a second sidewall of the second gate in the first direction and measured from an outermost point of an outer surface of the second spacer structure to the second sidewall. The second spacer structure has a second thickness that is greater than the first thickness. The NMOS transistor is a pass-gate of a static random access memory (SRAM) cell, and the PMOS transistor is a pull-up of the SRAM cell.

公开(公告)号：US20240292592A1

公开(公告)日：2024-08-29

申请号：US18655833

申请日：2024-05-06

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Chuan Yang ,  Chia-Hao Pao ,  Yu-Kuan Lin ,  Lien-Jung Hung ,  Ping-Wei Wang ,  Shih-Hao Lin

IPC分类号： H10B10/00 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC分类号： H10B10/125 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

摘要： A semiconductor device according to the present disclosure includes a gate extension structure, a first source/drain feature and a second source/drain feature, a vertical stack of channel members extending between the first source/drain feature and the second source/drain feature along a direction, and a gate structure wrapping around each of the vertical stack of channel members. The gate extension structure is in direct contact with the first source/drain feature.

公开(公告)号：US12009428B2

公开(公告)日：2024-06-11

申请号：US17812874

申请日：2022-07-15

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Chuan Yang ,  Kuo-Hsiu Hsu ,  Feng-Ming Chang ,  Kian-Long Lim ,  Lien Jung Hung

IPC分类号： H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L29/16 ,  H01L29/417 ,  H01L29/66

CPC分类号： H01L29/785 ,  H01L27/0886 ,  H01L29/0665 ,  H01L29/16 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/66818

摘要： A semiconductor device including nanosheet field-effect transistors (NSFETs) in a first region and fin field-effect transistors (FinFETs) in a second region and methods of forming the same are disclosed. In an embodiment, a device includes a first memory cell, the first memory cell including a first transistor including a first channel region, the first channel region including a first plurality of semiconductor nanostructures; and a second transistor including a second channel region, the second channel region including a semiconductor fin.

公开(公告)号：US20220367482A1

公开(公告)日：2022-11-17

申请号：US17814279

申请日：2022-07-22

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wen-Chun Keng ,  Kuo-Hsiu Hsu ,  Chih-Chuan Yang ,  Lien Jung Hung ,  Ping-Wei Wang

IPC分类号： H01L27/11 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/764

摘要： A semiconductor device according to the present disclosure includes a first source/drain feature, a second source/drain feature, a third source/drain feature, a first dummy fin disposed between the first source/drain feature and the second source/drain feature along a direction to isolate the first source/drain feature from the second source/drain feature, and a second dummy fin disposed between the second source/drain feature and the third source/drain feature along the direction to isolate the second source/drain feature from the third source/drain feature. The first dummy fin includes an outer dielectric layer, an inner dielectric layer over the outer dielectric layer, and a first capping layer disposed over the outer dielectric layer and the inner dielectric layer. The second dummy fin includes a base portion and a second capping layer disposed over the base portion.

公开(公告)号：US20220367481A1

公开(公告)日：2022-11-17

申请号：US17874463

申请日：2022-07-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Chuan Yang ,  Kuo-Hsiu Hsu ,  Feng-Ming Chang ,  Wen-Chun Keng ,  Lien Jung Hung

IPC分类号： H01L27/11

摘要： A method of forming a semiconductor device includes providing a substrate including a circuit region and a well strap region, forming a mandrel extending from the circuit region to the well strap region, depositing mandrel spacers on sidewalls of the mandrel, removing the mandrel in the circuit region, while the mandrel in the well strap region remains intact, patterning the substrate with the mandrel spacers in the circuit region and the mandrel in the well strap region as an etch mask, thereby forming at least a first fin in the circuit region and a second fin in the well strap region, and epitaxially growing a first epitaxial feature over the first fin in the circuit region and a second epitaxial feature over the second fin in the well strap region. A width of the second fin is larger than a width of the first fin.

公开(公告)号：US20220367459A1

公开(公告)日：2022-11-17

申请号：US17874421

申请日：2022-07-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Chuan Yang ,  Yu-Kuan Lin

IPC分类号： H01L27/092 ,  H01L29/08 ,  H01L29/10 ,  H01L21/8238 ,  H01L21/308 ,  H01L29/66 ,  H01L21/3065

摘要： A method includes forming an anti-punch-through layer over a first region and a second region of a substrate, forming a semiconductor layer over the anti-punch-through layer, patterning the semiconductor layer and the anti-punch-through layer to form a first plurality of fins over the first region and a second plurality of fins over the second region, and forming a patterned resist layer over the first plurality of fins and the second plurality of fins. The method also includes recessing a portion of the substrate between the first plurality of fins and the second plurality of fins in an etching process through openings of the patterned resist layer.

公开(公告)号：US20220352371A1

公开(公告)日：2022-11-03

申请号：US17811988

申请日：2022-07-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Chuan Yang ,  Shih-Hao Lin

IPC分类号： H01L29/78 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/165 ,  H01L29/267 ,  H01L29/10 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/311 ,  H01L27/092

摘要： Nanostructure field-effect transistors (NSFETs) including isolation layers formed between epitaxial source/drain regions and semiconductor substrates and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate; a gate stack over the semiconductor substrate, the gate stack including a gate electrode and a gate dielectric layer; a first epitaxial source/drain region adjacent the gate stack; and a high-k dielectric layer extending between the semiconductor substrate and the first epitaxial source/drain region, the high-k dielectric layer contacting the first epitaxial source/drain region, the gate dielectric layer and the high-k dielectric layer including the same material.

公开(公告)号：US11329168B2

公开(公告)日：2022-05-10

申请号：US16945298

申请日：2020-07-31

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Chuan Yang ,  Kuo-Hsiu Hsu

IPC分类号： H01L21/02 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/11 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786

摘要： Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a first semiconductor stack and a second semiconductor stack over a substrate, wherein each of the first and second semiconductor stacks includes semiconductor layers stacked up and separated from each other; a dummy spacer between the first and second semiconductor stacks, wherein the dummy spacer contacts a first sidewall of each semiconductor layer of the first and second semiconductor stacks; and a gate structure wrapping a second sidewall, a top surface, and a bottom surface of each semiconductor layer of the first and second semiconductor stacks.

公开(公告)号：US20210408012A1

公开(公告)日：2021-12-30

申请号：US16915609

申请日：2020-06-29

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wen-Chun Keng ,  Kuo-Hsiu Hsu ,  Chih-Chuan Yang ,  Lien Jung Hung ,  Ping-Wei Wang

IPC分类号： H01L27/11 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/764 ,  H01L21/8238 ,  H01L29/66

摘要： A semiconductor device according to the present disclosure includes a first source/drain feature, a second source/drain feature, a third source/drain feature, a first dummy fin disposed between the first source/drain feature and the second source/drain feature along a direction to isolate the first source/drain feature from the second source/drain feature, and a second dummy fin disposed between the second source/drain feature and the third source/drain feature along the direction to isolate the second source/drain feature from the third source/drain feature. The first dummy fin includes an outer dielectric layer, an inner dielectric layer over the outer dielectric layer, and a first capping layer disposed over the outer dielectric layer and the inner dielectric layer. The second dummy fin includes a base portion and a second capping layer disposed over the base portion.

公开(公告)号：US11043595B2

公开(公告)日：2021-06-22

申请号：US16441217

申请日：2019-06-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsin-Wen Su ,  Yu-Kuan Lin ,  Chih-Chuan Yang ,  Chang-Ta Yang ,  Shih-Hao Lin

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L21/762

摘要： A semiconductor device includes a memory macro having first and second well pick-up (WPU) areas along first and second edges of the memory macro, respectively, and memory bit areas between the first and the second WPU areas. The first and second WPU areas are oriented lengthwise generally along a first direction. In each of the first and second WPU areas, the memory macro includes n-type wells and p-type wells arranged alternately along the first direction with a well boundary between each of the n-type wells and the adjacent p-type well. The memory macro further includes active regions; an isolation structure; gate structures, and a first dielectric layer that is disposed at each of the well boundaries. From a top view, the first dielectric layer extends generally along a second direction perpendicular to the first direction and through all the gate structures in the first and the second WPU areas.