公开(公告)号：US20230030411A1

公开(公告)日：2023-02-02

申请号：US17967499

申请日：2022-10-17

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chia-Hung CHU ,  Sung-Li WANG ,  Fang-Wei LEE ,  Jung-Hao CHANG ,  Mrunal Abhijith KHADERBAD ,  Keng-Chu LIN

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L21/311 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/45 ,  H01L29/08 ,  H01L21/762 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/308 ,  H01L21/027 ,  H01L21/3213

摘要： A fin field effect transistor device structure includes a fin structure formed over a substrate. The fin field effect transistor device structure also includes a source/drain epitaxial structure formed over the fin structure. The fin field effect transistor device structure also includes a contact structure with a concave top surface formed over the source/drain epitaxial structure. The fin field effect transistor device structure also includes a barrier layer conformally wrapped around the contact structure. The fin field effect transistor device structure also includes a via structure formed over the contact structure. The concave top surface of the contact structure is below the top surface of the barrier layer.

公开(公告)号：US20140268449A1

公开(公告)日：2014-09-18

申请号：US14015945

申请日：2013-08-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chia-Hung CHU ,  Kuo-Ji CHEN

IPC分类号： H02H9/04

CPC分类号： H02H9/046

摘要： A device includes a first power node, a second power node, a first input node, a second input node, a protected circuit, and a switch circuit. The protected circuit is coupled between the first power node and the second power node, and the protected circuit is further coupled with the second input node. The switch circuit is coupled with the first power node, the second power node, the first input node, and the second input node. The switch circuit is configured to electrically decouple the first input node and the second input node after (a) the first power node is floating or electrically coupled to the second power node and (b) a voltage level at the first input node is greater than a voltage level at the second power node by a predetermined voltage value.

摘要翻译： 一种设备包括第一功率节点，第二功率节点，第一输入节点，第二输入节点，保护电路和开关电路。 受保护电路耦合在第一功率节点和第二功率节点之间，并且受保护的电路进一步与第二输入节点耦合。 开关电路与第一功率节点，第二功率节点，第一输入节点和第二输入节点耦合。 开关电路被配置为在（a）第一功率节点浮动或电耦合到第二功率节点之后电隔离第一输入节点和第二输入节点，并且（b）第一输入节点处的电压电平大于 在第二功率节点处的电压电平达预定电压值。

公开(公告)号：US20240274687A1

公开(公告)日：2024-08-15

申请号：US18647521

申请日：2024-04-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Hung CHU ,  Kan-Ju Lin ,  Hsu-Kai Chang ,  Chien Chang ,  Tzu-Pei Chen ,  Hung-Yi Huang ,  Sung-Li Wang ,  Shuen-Shin Liang

IPC分类号： H01L29/45 ,  H01L21/311 ,  H01L21/8234 ,  H01L23/532 ,  H01L23/535 ,  H01L29/40 ,  H01L29/417

CPC分类号： H01L29/45 ,  H01L21/31116 ,  H01L21/823475 ,  H01L23/53242 ,  H01L23/535 ,  H01L29/401 ,  H01L29/41791

摘要： The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a gate structure over the substrate, a layer of dielectric material over the gate structure, a source/drain (S/D) contact layer formed through and adjacent to the gate structure, and a trench conductor layer over and in contact with the S/D contact layer. The S/D contact layer can include a layer of platinum-group metallic material and a silicide layer formed between the substrate and the layer of platinum-group metallic material. A top width of a top portion of the layer of platinum-group metallic material can be greater than or substantially equal to a bottom width of a bottom portion of the layer of platinum-group metallic material.

公开(公告)号：US20230402366A1

公开(公告)日：2023-12-14

申请号：US17836781

申请日：2022-06-09

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shuen-Shin LIANG ,  Chia-Hung CHU ,  Po-Chin CHANG ,  Hsu-Kai CHANG ,  Kuan-Kan HU ,  Ken-Yu CHANG ,  Hung-Yi HUANG ,  Harry CHIEN ,  Wei-Yip LOH ,  Chun-I TSAI ,  Hong-Mao LEE ,  Sung-Li WANG ,  Pinyen LIN ,  Chuan-Hui SHEN

IPC分类号： H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L23/53266 ,  H01L21/76843 ,  H01L21/76883

摘要： A semiconductor device includes a substrate, a source/drain region disposed in the substrate, a silicide structure disposed on the source/drain region, a first dielectric layer disposed over the substrate, a conductive contact disposed in the first dielectric layer and over the silicide structure, a second dielectric layer disposed over the first dielectric layer, a via contact disposed in the second dielectric layer and connected to the conductive contact, and a first metal surrounding the via contact.

公开(公告)号：US20230253308A1

公开(公告)日：2023-08-10

申请号：US17668482

申请日：2022-02-10

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chia-Hung CHU ,  Po-Chin CHANG ,  Tzu-Pei CHEN ,  Yuting CHENG ,  Kan-Ju LIN ,  Chih-Shiun CHOU ,  Hung-Yi HUANG ,  Pinyen LIN ,  Sung-Li WANG ,  Sheng-Tsung WANG ,  Lin-Yu HUANG ,  Shao-An WANG ,  Harry CHIEN

IPC分类号： H01L23/522 ,  H01L23/528 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L23/5283 ,  H01L21/76816 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76871 ,  H01L29/41775

摘要： A method for manufacturing a semiconductor device includes forming a conductive feature in a first dielectric layer; forming a second dielectric layer on the first dielectric layer; forming a trench that penetrates through the second dielectric layer, and terminates at the conductive feature; forming a contact layer in the trench and on the conductive feature; etching back the contact layer to form a first via contact feature in the trench, the first via contact feature being electrically connected to the conductive feature; and forming a second via contact feature on the first via contact feature in the trench.

公开(公告)号：US20220375868A1

公开(公告)日：2022-11-24

申请号：US17875242

申请日：2022-07-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Cheng-Wei CHANG ,  Chia-Hung CHU ,  Kao-Feng LIN ,  Hsu-Kai CHANG ,  Shuen-Shin LIANG ,  Sung-Li WANG ,  Yi-Ying LIU ,  Po-Nan YEH ,  Yu Shih WANG ,  U-Ting CHIU ,  Chun-Neng LIN ,  Ming-Hsi YEH

IPC分类号： H01L23/532 ,  H01L23/522 ,  H01L21/768

摘要： A semiconductor device includes a gate electrode, a source/drain structure, a lower contact contacting either of the gate electrode or the source/drain structure, and an upper contact disposed in an opening formed in an interlayer dielectric (ILD) layer and in direct contact with the lower contact. The upper contact is in direct contact with the ILD layer without an interposing conductive barrier layer, and the upper contact includes ruthenium.

公开(公告)号：US20230230916A1

公开(公告)日：2023-07-20

申请号：US17577800

申请日：2022-01-18

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shuen-Shin LIANG ,  Chia-Hung CHU ,  Po-Chin CHANG ,  Tzu-Pei CHEN ,  Ken-Yu CHANG ,  Hung-Yi HUANG ,  Harry CHIEN ,  Wei-Yip LOH ,  Chun-I TSAI ,  Hong-Mao LEE ,  Sung-Li WANG ,  Pinyen LIN

IPC分类号： H01L23/522 ,  H01L29/40 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L29/401 ,  H01L21/76877 ,  H01L21/76843

摘要： A method for manufacturing a semiconductor device includes: forming a lower metal contact in a trench of a first dielectric structure, the lower metal contact having a height less than a depth of the trench and being made of a first metal material; forming an upper metal contact to fill the trench and to be in contact with the lower metal contact, the upper metal contact being formed of a second metal material different from the first metal material and having a bottom surface with a dimension the same as a dimension of a top surface of the lower metal contact; forming a second dielectric structure on the first dielectric structure; and forming a via contact penetrating through the second dielectric structure to be electrically connected to the upper metal contact, the via contact being formed of a metal material the same as the second metal material.

公开(公告)号：US20240332393A1

公开(公告)日：2024-10-03

申请号：US18741963

申请日：2024-06-13

申请人： Taiwan Semiconductor Manufacturing Company, LTD.

发明人： Hsu-Kai CHANG ,  Jhih-Rong HUANG ,  Yen-Tien TUNG ,  Chia-Hung CHU ,  Shuen-Shin LIANG ,  Tzer-Min SHEN ,  Pinyen LIN ,  Sung-Li WANG

IPC分类号： H01L29/45 ,  H01L21/285 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/45 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7851

摘要： A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second gate structures disposed on first and second fin structures, first and second source/drain (S/D) regions disposed on the first and second fin structures, first and second contact structures disposed on the first and second S/D regions, and a dipole layer disposed at an interface between the first nWFM silicide layer and the first S/D region. The first contact structure includes a first nWFM silicide layer disposed on the first S/D region and a first contact plug disposed on the first nWFM silicide layer. The second contact structure includes a pWFM silicide layer disposed on the second S/D region, a second nWFM silicide layer disposed on the pWFM silicide layer, and a second contact plug disposed on the pWFM silicide layer.

公开(公告)号：US20240313075A1

公开(公告)日：2024-09-19

申请号：US18182921

申请日：2023-03-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shuen-Shin LIANG ,  Kan-Ju LIN ,  Chia-Hung CHU ,  Chien CHANG ,  Harry CHIEN ,  Sung-Li WANG

IPC分类号： H01L29/423 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L29/42392 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

摘要： The present disclosure provides a method for semiconductor fabrication. The method includes depositing a first metal layer by a first deposition over a source/drain (S/D) feature and over side portions of a trench exposing the S/D feature. The first metal layer is thicker over the S/D feature than over side portions of the trench. The method includes growing a metal on the first metal layer by a second deposition to form a second metal layer filling up the trench. The second deposition is different from the first deposition and the growing of the metal in a vertical direction is grown at a faster rate than the growing of the metal in a horizontal direction. After growing the metal to form the second metal layer, the method includes planarizing the first and second metal layers to form an S/D contact. The method forms an S/D via on the second metal layer.

公开(公告)号：US20230299168A1

公开(公告)日：2023-09-21

申请号：US17695075

申请日：2022-03-15

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Kuan-Kan HU ,  Shuen-Shin LIANG ,  Chia-Hung CHU ,  Po-Chin CHANG ,  Hsu-Kai CHANG ,  Ken-Yu CHANG ,  Wei-Yip LOH ,  Hung-Yi HUANG ,  Harry CHIEN ,  Sung-Li WANG ,  Pinyen LIN ,  Chuan-Hui SHEN ,  Tzu-Pei CHEN ,  Yuting CHENG

IPC分类号： H01L29/45 ,  H01L29/40 ,  H01L29/417

CPC分类号： H01L29/45 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/41733 ,  H01L23/5226

摘要： A semiconductor device includes a semiconductor substrate, an epitaxial structure, a silicide structure, a conductive structure, and a protection segment. The epitaxial structure is disposed in the semiconductor substrate. The silicide structure is disposed in the epitaxial structure. The conductive structure is disposed over the silicide structure and is electrically connected to the silicide structure. The protection segment is made of metal nitride, is disposed over the silicide structure, and is disposed between the silicide structure and the conductive structure.