公开(公告)号：US20230327002A1

公开(公告)日：2023-10-12

申请号：US17714630

申请日：2022-04-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chieh-Wei CHEN ,  Jian-Jou LIAN ,  Tzu-Ang CHIANG ,  Po-Yuan WANG ,  Yu-Shih WANG ,  Chun-Neng LIN ,  Ming-Hsi YEH

IPC: H01L29/66 ,  H01L29/40

CPC classification number: H01L29/66795 ,  H01L29/66545 ,  H01L29/401 ,  H01L29/4236

Abstract: A method of forming a semiconductor device includes: forming a semiconductor structure having source/drain regions, a fin disposed between the source/drain regions, and a dummy gate disposed on the fin and surrounded by a spacer; removing the dummy gate to form a gate trench which is defined by a trench-defining wall; forming a gate dielectric layer on the trench-defining wall; forming a work function structure on the gate dielectric layer; forming a resist layer to fill the gate trench; removing a top portion of the resist layer; removing the work function structure exposed from the resist layer using a wet chemical etchant; removing the resist layer; and forming a conductive gate in the gate trench.

公开(公告)号：US20240371962A1

公开(公告)日：2024-11-07

申请号：US18772679

申请日：2024-07-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： U-Ting CHIU ,  Chun-Cheng CHOU ,  Chi-Shin WANG ,  Chun-Neng LIN ,  Ming-Hsi YEH

IPC: H01L29/45 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/528 ,  H01L29/417

Abstract: In some implementations, fluorine is oxidized after dry etching an oxide layer above a source/drain contact and before cleaning. Accordingly, less hydrofluoric acid is formed during cleaning, which reduces unexpected wet etching of the source/drain contact. This allows for forming a recess in the source/drain contact with a depth to width ratio in a range from approximately 1.0 to approximately 1.4 and prevents damage to a layer of silicide below the source/drain that can be caused by excessive hydrofluoric acid. Additionally, or alternatively, the recess is formed using multiple wet etch processes, and any residual fluorine is oxidized between the wet etch processes. Accordingly, each wet etching process may be shorter and less corrosive, which allows for greater control over dimensions of the recess. Additionally, less hydrofluoric acid may be formed during cleaning processes between the wet etch processes, which reduces the etching of the source/drain contact between processes.

公开(公告)号：US20220375868A1

公开(公告)日：2022-11-24

申请号：US17875242

申请日：2022-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Cheng-Wei CHANG ,  Chia-Hung CHU ,  Kao-Feng LIN ,  Hsu-Kai CHANG ,  Shuen-Shin LIANG ,  Sung-Li WANG ,  Yi-Ying LIU ,  Po-Nan YEH ,  Yu Shih WANG ,  U-Ting CHIU ,  Chun-Neng LIN ,  Ming-Hsi YEH

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768

Abstract: A semiconductor device includes a gate electrode, a source/drain structure, a lower contact contacting either of the gate electrode or the source/drain structure, and an upper contact disposed in an opening formed in an interlayer dielectric (ILD) layer and in direct contact with the lower contact. The upper contact is in direct contact with the ILD layer without an interposing conductive barrier layer, and the upper contact includes ruthenium.

公开(公告)号：US20230411206A1

公开(公告)日：2023-12-21

申请号：US17841901

申请日：2022-06-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chun-Neng LIN ,  Jian-Jou LIAN ,  Chieh-Wei CHEN

IPC: H01L21/768 ,  H01L23/522 ,  H01L29/66 ,  H01L21/311

CPC classification number: H01L21/76802 ,  H01L21/76877 ,  H01L23/5226 ,  H01L29/66803 ,  H01L21/31111

Abstract: A method for manufacturing a semiconductor device includes: forming a patterned dielectric layer over a substrate, the patterned dielectric layer including an interconnect opening having a sidewall surface and a bottom surface; and forming a doped film by an opening-adjustment process, the doped film being disposed on the patterned dielectric layer and extending into the interconnect opening to cover an upper portion of the sidewall surface, so as to adjust a profile of the interconnect opening.

公开(公告)号：US20220336615A1

公开(公告)日：2022-10-20

申请号：US17446218

申请日：2021-08-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： U-Ting CHIU ,  Chun-Cheng CHOU ,  Chi-Shin WANG ,  Chun-Neng LIN ,  Ming-Hsi YEH

IPC: H01L29/45 ,  H01L23/528 ,  H01L29/417 ,  H01L21/311 ,  H01L21/768 ,  H01L21/3213

Abstract: In some implementations, fluorine is oxidized after dry etching an oxide layer above a source/drain contact and before cleaning. Accordingly, less hydrofluoric acid is formed during cleaning, which reduces unexpected wet etching of the source/drain contact. This allows for forming a recess in the source/drain contact with a depth to width ratio in a range from approximately 1.0 to approximately 1.4 and prevents damage to a layer of silicide below the source/drain that can be caused by excessive hydrofluoric acid. Additionally, or alternatively, the recess is formed using multiple wet etch processes, and any residual fluorine is oxidized between the wet etch processes. Accordingly, each wet etching process may be shorter and less corrosive, which allows for greater control over dimensions of the recess. Additionally, less hydrofluoric acid may be formed during cleaning processes between the wet etch processes, which reduces the etching of the source/drain contact between processes.