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公开(公告)号：US12062614B2
公开(公告)日：2024-08-13
申请号：US17374327
申请日：2021-07-13
发明人： John Bruley , Jack O. Chu , Kam-Leung Lee , Ahmet S. Ozcan , Paul M. Solomon , Jeng-Bang Yau
IPC分类号： H01L23/535 , C22C30/00 , H01L21/285 , H01L21/768 , H01L23/485 , H01L23/532 , H01L29/78
CPC分类号： H01L23/535 , C22C30/00 , H01L21/28518 , H01L21/2855 , H01L21/76805 , H01L21/76843 , H01L21/76846 , H01L21/76858 , H01L21/76864 , H01L21/76895 , H01L23/485 , H01L23/53223 , H01L23/53266 , H01L29/7851 , H01L23/53209 , H01L23/53238 , H01L23/53252
摘要： A method of forming a contact to a semiconductor device is provided that forms an alloy composed of nickel (Ni), platinum (Pt), aluminum (Al), titanium (Ti) and a semiconductor material. The methods may include forming a nickel and platinum semiconductor alloy at a base of a via. A titanium layer having an angstrom scale thickness is deposited in the via in contact with the nickel platinum semiconductor alloy. An aluminum containing fill is deposited atop the titanium layer. A forming gas anneal including an oxygen containing atmosphere is applied to the structure to provide a contact alloy comprising nickel, platinum, aluminum, titanium and a semiconductor element from the contact surface of the semiconductor device.
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公开(公告)号：US11862567B2
公开(公告)日：2024-01-02
申请号：US17196267
申请日：2021-03-09
发明人： John Bruley , Jack O. Chu , Kam-Leung Lee , Ahmet S. Ozcan , Paul M. Solomon , Jeng-bang Yau
IPC分类号： H01L23/535 , H01L23/532 , H01L29/78 , H01L21/768 , C22C30/00 , H01L23/485 , H01L21/285
CPC分类号： H01L23/535 , C22C30/00 , H01L21/2855 , H01L21/28518 , H01L21/76805 , H01L21/76843 , H01L21/76846 , H01L21/76858 , H01L21/76864 , H01L21/76895 , H01L23/485 , H01L23/53223 , H01L23/53266 , H01L29/7851 , H01L23/53209 , H01L23/53238 , H01L23/53252
摘要： A method of forming a contact to a semiconductor device is provided that forms an alloy composed of nickel (Ni), platinum (Pt), aluminum (Al), titanium (Ti) and a semiconductor material. The methods may include forming a nickel and platinum semiconductor alloy at a base of a via. A titanium layer having an angstrom scale thickness is deposited in the via in contact with the nickel platinum semiconductor alloy. An aluminum containing fill is deposited atop the titanium layer. A forming gas anneal including an oxygen containing atmosphere is applied to the structure to provide a contact alloy comprising nickel, platinum, aluminum, titanium and a semiconductor element from the contact surface of the semiconductor device.
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公开(公告)号：US10985105B2
公开(公告)日：2021-04-20
申请号：US16168092
申请日：2018-10-23
发明人： John Bruley , Jack O. Chu , Kam-Leung Lee , Ahmet S. Ozcan , Paul M. Solomon , Jeng-bang Yau
IPC分类号： H01L23/535 , H01L23/532 , H01L29/78 , H01L21/768 , C22C30/00 , H01L23/485 , H01L21/285
摘要： A method of forming a contact to a semiconductor device is provided that forms an alloy composed of nickel (Ni), platinum (Pt), aluminum (Al), titanium (Ti) and a semiconductor material. The methods may include forming a nickel and platinum semiconductor alloy at a base of a via. A titanium layer having an angstrom scale thickness is deposited in the via in contact with the nickel platinum semiconductor alloy. An aluminum containing fill is deposited atop the titanium layer. A forming gas anneal including an oxygen containing atmosphere is applied to the structure to provide a contact alloy comprising nickel, platinum, aluminum, titanium and a semiconductor element from the contact surface of the semiconductor device.
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公开(公告)号：US10685888B2
公开(公告)日：2020-06-16
申请号：US15334479
申请日：2016-10-26
IPC分类号： H01L21/8238 , H01L29/06 , H01L21/3215 , H01L21/265 , H01L21/285 , H01L29/45 , H01L29/66 , H01L27/092 , H01L21/84 , H01L27/12 , H01L29/16 , H01L29/161 , H01L29/24 , H01L29/423 , H01L29/786 , H01L21/768
摘要： A semiconductor structure and a method for fabricating the same. The semiconductor structure includes at least one semiconductor fin disposed on a substrate. A disposable gate contacts the at least one semiconductor fin. A spacer is disposed on the at least one semiconductor fin and in contact with the disposable gate. Epitaxially grown source and drain regions are disposed at least partially within the at least one semiconductor fin. A first one of silicide and germanide is disposed on and in contact with the source region. A second one of one of silicide and germanide is disposed on and in contact with the drain region. The method includes epitaxially growing source/drain regions within a semiconductor fin. A contact metal layer contacts the source/drain regions. One of a silicide and a germanide is formed on the source/drain regions from the contact metal layer prior to removing the disposable gate.
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公开(公告)号：US20200058758A1
公开(公告)日：2020-02-20
申请号：US16662782
申请日：2019-10-24
IPC分类号： H01L29/66 , H01L21/8234 , H01L21/285 , H01L29/78 , H01L29/417
摘要： A method for forming a salicide includes forming, on at least one semiconductor fin, at least one source/drain (S/D) region including a (111) facet and having a cross-sectional quadrilateral shape, forming a conductive material on the (111) facet, annealing the conductive material to form a silicide on the (111) facet, and forming at least one contact to the silicide.
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公开(公告)号：US20190305131A1
公开(公告)日：2019-10-03
申请号：US16442645
申请日：2019-06-17
发明人： Oleg Gluschenkov , Ahmet S. Ozcan
IPC分类号： H01L29/78 , H01L29/417 , H01L29/08 , H01L29/66
摘要： Described herein is a semiconductor structure and method of manufacture. The semiconductor structure includes a plurality of semiconductor fins on a substrate and a plurality of raised active regions, wherein each raised active region is located on sidewalls of a corresponding semiconductor fin among said plurality of semiconductor fins. The raised active regions are laterally spaced from any other of the raised active regions. Each raised active region comprises angled sidewall surfaces that are not parallel or perpendicular to a topmost horizontal surface of said substrate. The raised active regions are silicon germanium (SiGe). The semiconductor structure includes a metal semiconductor alloy region contacting at least said angled sidewall surfaces of at least two adjacent raised active regions. The semiconductor alloy region includes a material selected from the group consisting of nickel silicide, nickel-platinum silicide and cobalt silicide.
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公开(公告)号：US20190157203A1
公开(公告)日：2019-05-23
申请号：US16258041
申请日：2019-01-25
发明人： John Bruley , Jack O. Chu , Kam-Leung Lee , Ahmet S. Ozcan , Paul M. Solomon , Jeng-bang Yau
IPC分类号： H01L23/535 , C22C30/00 , H01L21/768 , H01L23/532 , H01L29/78
摘要： A method of forming a contact to a semiconductor device is provided that forms an alloy composed of nickel (Ni), platinum (Pt), aluminum (Al), titanium (Ti) and a semiconductor material. The methods may include forming a nickel and platinum semiconductor alloy at a base of a via. A titanium layer having an angstrom scale thickness is deposited in the via in contact with the nickel platinum semiconductor alloy. An aluminum containing fill is deposited atop the titanium layer. A forming gas anneal including an oxygen containing atmosphere is applied to the structure to provide a contact alloy comprising nickel, platinum, aluminum, titanium and a semiconductor element from the contact surface of the semiconductor device.
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公开(公告)号：US10249529B2
公开(公告)日：2019-04-02
申请号：US14969670
申请日：2015-12-15
IPC分类号： H01L21/762 , H01L29/06 , H01L21/02 , H01L21/3115 , H01L21/321 , H01L21/3205 , H01L21/265 , H01L21/324 , H01L21/8234 , H01L27/092 , H01L29/161 , H01L29/167 , H01L21/84 , H01L27/12 , H01L21/8238
摘要： A method of making a channel region in a semiconductor device includes providing a substrate having a first transistor area arranged adjacent to a second transistor area; growing an epitaxial layer on the second transistor area of the substrate; forming a trench in the substrate between the first transistor area and the second transistor area; performing a condensation technique to thermally mix materials of the epitaxial layer and the substrate; and filling the trench with a dielectric material to form a shallow trench isolation region between a first channel region of the first transistor and a second channel region of the second transistor; wherein performing the condensation technique is performed after forming the trench.
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公开(公告)号：US10243046B2
公开(公告)日：2019-03-26
申请号：US15798457
申请日：2017-10-31
IPC分类号： H01L21/00 , H01L21/782 , H01L29/66 , H01L29/786 , H01L29/06 , H01L29/10 , H01L29/78 , H01L29/161 , H01L29/08 , H01L29/423
摘要： A p-type metal-oxide-semiconductor (pMOS) planar fully depleted silicon-on-insulator (FDSOI) device and a method of fabricating the pMOS FDSOI are described. The method includes processing a silicon germanium (SiGe) layer disposed on an insulator layer to form gaps on a surface opposite a surface that is disposed on the insulator layer, each of the gaps extending into the SiGe layer to a depth less than or equal to a thickness of the SiGe layer, and forming a gate conductor over a region of the SiGe layer corresponding to a channel region of the pMOS. The method also includes performing an epitaxial process on the SiGe layer at locations corresponding to source and drain regions of the pMOS planar FDSOI device.
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公开(公告)号：US10147676B1
公开(公告)日：2018-12-04
申请号：US15595141
申请日：2017-05-15
发明人： Charles E. Cox , Harald Huels , Arvind Kumar , Xiao Hu Liu , Ahmet S. Ozcan , Winfried W. Wilcke
IPC分类号： H01L21/44 , H01L23/34 , H01L23/50 , H01L23/498 , H01L23/00 , H01L25/065 , H01L25/00 , H01L21/48
摘要： A method is provided to supply power to wafer-scale ICs. The method includes receiving a wafer containing ICs placed on the top of the wafer. The wafer has through-hole vias to provide power from the bottom to the ICs. The method also includes a printed circuit board, which has power rails in a pattern on the top of the printed circuit board, where the rails provide voltage and ground. The method continues with placing metal solder spheres between the bottom of the wafer and the top of the printed circuit board, where the spheres provide connections between the two, and where the spheres are free to move and operate as mechanical springs to resist clamping forces. The method also includes applying clamping pressure to the structure to establish connections by compressing the spheres, where no soldering is required.
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