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公开(公告)号：US11961762B2
公开(公告)日：2024-04-16
申请号：US17809960
申请日：2022-06-30
发明人： Ming-Da Cheng , Tzy-Kuang Lee , Song-Bor Lee , Wen-Hsiung Lu , Po-Hao Tsai , Wen-Che Chang
IPC分类号： H01L21/768 , H01L23/00
CPC分类号： H01L21/76885 , H01L21/76802 , H01L21/76852 , H01L21/76871 , H01L24/05 , H01L24/13 , H01L24/32 , H01L2224/0231 , H01L2224/02331 , H01L2224/0235 , H01L2224/0239 , H01L2224/0391 , H01L2224/0401 , H01L2224/05008 , H01L2224/05022
摘要： A method includes forming a first conductive feature, depositing a passivation layer on a sidewall and a top surface of the first conductive feature, etching the passivation layer to reveal the first conductive feature, and recessing a first top surface of the passivation layer to form a step. The step comprises a second top surface of the passivation layer. The method further includes forming a planarization layer on the passivation layer, and forming a second conductive feature extending into the passivation layer to contact the first conductive feature.
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公开(公告)号：US20220336276A1
公开(公告)日：2022-10-20
申请号：US17809960
申请日：2022-06-30
发明人： Ming-Da Cheng , Tzy-Kuang Lee , Song-Bor Lee , Wen-Hsiung Lu , Po-Hao Tsai , Wen-Che Chang
IPC分类号： H01L21/768 , H01L23/00
摘要： A method includes forming a first conductive feature, depositing a passivation layer on a sidewall and a top surface of the first conductive feature, etching the passivation layer to reveal the first conductive feature, and recessing a first top surface of the passivation layer to form a step. The step comprises a second top surface of the passivation layer. The method further includes forming a planarization layer on the passivation layer, and forming a second conductive feature extending into the passivation layer to contact the first conductive feature.
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公开(公告)号：US20210375675A1
公开(公告)日：2021-12-02
申请号：US17085731
申请日：2020-10-30
发明人： Ming-Da Cheng , Tzy-Kuang Lee , Song-Bor Lee , Wen-Hsiung Lu , Po-Hao Tsai , Wen-Che Chang
IPC分类号： H01L21/768 , H01L23/00
摘要： A method includes forming a first conductive feature, depositing a passivation layer on a sidewall and a top surface of the first conductive feature, etching the passivation layer to reveal the first conductive feature, and recessing a first top surface of the passivation layer to form a step. The step comprises a second top surface of the passivation layer. The method further includes forming a planarization layer on the passivation layer, and forming a second conductive feature extending into the passivation layer to contact the first conductive feature.
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公开(公告)号：US11152319B2
公开(公告)日：2021-10-19
申请号：US16871032
申请日：2020-05-10
发明人： Wen-Hsiung Lu , Chen-Shien Chen , Chen-En Yen , Cheng-Jen Lin , Chin-Wei Kang , Kai-Jun Zhan
摘要： A micro-connection structure is provided. The micro-connection structure includes an under bump metallurgy (UBM) pad, a bump and an insulating ring. The UBM pad is electrically connected to at least one metallic contact of a substrate. The bump is disposed on the UBM pad and electrically connected with the UBM pad. The insulating ring surrounds the bump and the UBM pad. The bump is separate from the insulating ring with a distance and the bump is isolated by a gap between the insulating ring and the bump.
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公开(公告)号：US11101233B1
公开(公告)日：2021-08-24
申请号：US16868909
申请日：2020-05-07
发明人： Chen-En Yen , Chin-Wei Kang , Kai-Jun Zhan , Wen-Hsiung Lu , Cheng-Jen Lin , Ming-Da Cheng , Mirng-Ji Lii
IPC分类号： H01L21/48 , H01L23/552 , H01L23/00
摘要： A method for forming a semiconductor device is provided. The method includes providing a substrate. The method includes forming a mask layer over a surface of the substrate. The mask layer has an opening over a portion of the surface. The method includes depositing a conductive layer over the surface and the mask layer. The method includes removing the mask layer and the conductive layer over the mask layer. The conductive layer remaining after the removal of the mask layer and the conductive layer over the mask layer forms a conductive pad. The method includes bonding a device to the conductive pad through a solder layer. The conductive pad is embedded in the solder layer.
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公开(公告)号：US20190259719A1
公开(公告)日：2019-08-22
申请号：US16403631
申请日：2019-05-06
发明人： Wen-Hsiung Lu , Chen-Shien Chen , Chen-En Yen , Cheng-Jen Lin , Chin-Wei Kang , Kai-Jun Zhan
IPC分类号： H01L23/00
摘要： A micro-connection structure is provided. The micro-connection structure includes an under bump metallurgy (UBM) pad, a bump and an insulating ring. The UBM pad is electrically connected to at least one metallic contact of a substrate. The bump is disposed on the UBM pad and electrically connected with the UBM pad. The insulating ring surrounds the bump and the UBM pad. The bump is separate from the insulating ring with a distance and the bump is isolated by a gap between the insulating ring and the bump.
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公开(公告)号：US20180012860A1
公开(公告)日：2018-01-11
申请号：US15712680
申请日：2017-09-22
发明人： Hung-Jen Lin , Tsung-Ding Wang , Chien-Hsiun Lee , Wen-Hsiung Lu , Ming-Da Cheng , Chung-Shi Liu
IPC分类号： H01L23/00 , H01L21/768 , H01L23/31 , H01L21/56 , H01L23/525
CPC分类号： H01L24/81 , H01L21/563 , H01L21/565 , H01L21/566 , H01L21/768 , H01L23/3114 , H01L23/3171 , H01L23/525 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/27 , H01L24/29 , H01L24/83 , H01L24/92 , H01L24/94 , H01L2224/02311 , H01L2224/0239 , H01L2224/024 , H01L2224/0347 , H01L2224/03612 , H01L2224/03614 , H01L2224/0362 , H01L2224/0401 , H01L2224/05008 , H01L2224/05073 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05187 , H01L2224/05582 , H01L2224/05611 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05681 , H01L2224/11334 , H01L2224/1146 , H01L2224/11849 , H01L2224/13022 , H01L2224/131 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/21 , H01L2224/27318 , H01L2224/27334 , H01L2224/27416 , H01L2224/2919 , H01L2224/73204 , H01L2224/81024 , H01L2224/81191 , H01L2224/81203 , H01L2224/81801 , H01L2224/81815 , H01L2224/83192 , H01L2224/83855 , H01L2224/92125 , H01L2224/94 , H01L2924/00014 , H01L2924/01013 , H01L2924/01047 , H01L2924/12042 , H01L2924/181 , H01L2924/2076 , H01L2224/81 , H01L2924/01029 , H01L2924/04941 , H01L2924/04953 , H01L2924/014 , H01L2224/11 , H01L2924/00
摘要： In some embodiments, the present disclosure relates to a package assembly having a bump on a first substrate. A molding compound is on the first substrate and contacts sidewalls of the bump. A no-flow underfill layer is on a conductive region of a second substrate. The no-flow underfill layer and the conductive region contact the bump. A mask layer is arranged on the second substrate and laterally surrounds the no-flow underfill layer. The no-flow underfill layer contacts the substrate between the conductive region and the mask layer.
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公开(公告)号：US12009256B2
公开(公告)日：2024-06-11
申请号：US18338095
申请日：2023-06-20
发明人： Ming-Da Cheng , Wen-Hsiung Lu , Chin Wei Kang , Yung-Han Chuang , Lung-Kai Mao , Yung-Sheng Lin
IPC分类号： H01L21/768 , H01L23/00
CPC分类号： H01L21/76885 , H01L21/76802 , H01L21/76852 , H01L21/76871 , H01L24/05 , H01L24/13 , H01L24/32 , H01L2224/0231 , H01L2224/02331 , H01L2224/0235 , H01L2224/0239 , H01L2224/0391 , H01L2224/0401 , H01L2224/05008 , H01L2224/05022
摘要： A method includes forming a metal seed layer over a first conductive feature of a wafer, forming a patterned photo resist on the metal seed layer, forming a second conductive feature in an opening in the patterned photo resist, and heating the wafer to generate a gap between the second conductive feature and the patterned photo resist. A protection layer is plated on the second conductive feature. The method further includes removing the patterned photo resist, and etching the metal seed layer.
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公开(公告)号：US11894241B2
公开(公告)日：2024-02-06
申请号：US17220339
申请日：2021-04-01
发明人： Mirng-Ji Lii , Chen-Shien Chen , Lung-Kai Mao , Ming-Da Cheng , Wen-Hsiung Lu
IPC分类号： H01L21/48 , H01L23/498 , H01L23/522 , H01L23/538 , H01L23/00
CPC分类号： H01L21/4857 , H01L21/486 , H01L21/4853 , H01L23/49816 , H01L23/49822 , H01L23/49838 , H01L23/5226 , H01L23/5383 , H01L24/80 , H01L2224/80345 , H01L2224/80355
摘要： A method includes forming a first package component, which formation process includes forming a first plurality of openings in a first dielectric layer, depositing a first metallic material into the first plurality of openings, performing a planarization process on the first metallic material and the first dielectric layer to form a plurality of metal pads in the first dielectric layer, and selectively depositing a second metallic material on the plurality of metal pads to form a plurality of bond pads. The first plurality of bond pads comprise the plurality of metal pads and corresponding parts of the second metallic material. The first package component is bonded to a second package component.
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公开(公告)号：US20240021499A1
公开(公告)日：2024-01-18
申请号：US18362559
申请日：2023-07-31
发明人： Hsu-Lun Liu , Wen-Hsiung Lu , Ming-Da Cheng , Chen-En Yen , Cheng-Lung Yang , Kuanchih Huang
IPC分类号： H01L23/48 , H01L23/60 , H01L21/768
CPC分类号： H01L23/481 , H01L23/60 , H01L21/76877 , H01L21/76898
摘要： Some devices included a substrate; and a through via, including a plurality of scallops adjacent the through via in a first region and a plurality of scallops adjacent the through via in a second region, the of scallops having a first depth, the scallops having a greater depth. Some devices include an opening extending into a substrate, including a first region and a second region. Sidewalls of the opening include a stack of first concave portions extending a first distance into the first substrate, and a stack of second concave portions extending a second distance, greater than and parallel to the first distance, into the first substrate. A conductor partially fills the first concave portions and at least partially fills the respective second concave portions.
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