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    Semiconductor memory
    1.
    发明授权
    Semiconductor memory 有权

    公开(公告)号：US09646992B2

    公开(公告)日：2017-05-09

    申请号：US15063115

    申请日：2016-03-07

    Applicant: Kabushiki Kaisha Toshiba

    Inventor： Atsushi Kawasumi

    IPC: H01L29/49 ,  H01L27/118

    CPC classification number: H01L27/11807 ,  H01L27/1104 ,  H01L27/11582 ,  H01L28/00 ,  H01L2027/11812 ,  H01L2027/11838 ,  H01L2027/11848 ,  H01L2027/11864 ,  H01L2027/11881

    Abstract: According to one embodiment, a semiconductor memory 100 includes a memory cell array 100A composed of a plurality of SRAM cells 10 including NMOS transistors and PMOS transistors, and a bias circuit 100B connected to a ground GND1 or power supply voltage VDD1 of the memory cell array 100A. The bias circuit 100B includes NMOS transistors 121, 122, 133 and 134 that are same as the NMOS transistors of the SRAM cells 10 in terms of channel length and channel width and in terms of dopant and dose amount at a channel portion, and PMOS transistors 111 and 112 that are same as the PMOS transistors of the SRAM cells 10 in terms of channel length and channel width and in terms of dopant and dose amount at a channel portion. Diffusion regions of the NMOS transistors and the PMOS transistors are formed in a same semiconductor layer.

    SEMICONDUCTOR MEMORY
    2.
    发明申请
    SEMICONDUCTOR MEMORY 有权
    半导体存储器

    公开(公告)号：US20170069659A1

    公开(公告)日：2017-03-09

    申请号：US15063115

    申请日：2016-03-07

    Applicant: Kabushiki Kaisha Toshiba

    Inventor： Atsushi KAWASUMI

    IPC: H01L27/118

    CPC classification number: H01L27/11807 ,  H01L27/1104 ,  H01L27/11582 ,  H01L28/00 ,  H01L2027/11812 ,  H01L2027/11838 ,  H01L2027/11848 ,  H01L2027/11864 ,  H01L2027/11881

    Abstract: According to one embodiment, a semiconductor memory 100 includes a memory cell array 100A composed of a plurality of SRAM cells 10 including NMOS transistors and PMOS transistors, and a bias circuit 100B connected to a ground GND1 or power supply voltage VDD1 of the memory cell array 100A. The bias circuit 100B includes NMOS transistors 121, 122, 133 and 134 that are same as the NMOS transistors of the SRAM cells 10 in terms of channel length and channel width and in terms of dopant and dose amount at a channel portion, and PMOS transistors 111 and 112 that are same as the PMOS transistors of the SRAM cells 10 in terms of channel length and channel width and in terms of dopant and dose amount at a channel portion. Diffusion regions of the NMOS transistors and the PMOS transistors are formed in a same semiconductor layer.

    Abstract translation: 根据一个实施例，半导体存储器100包括由包括NMOS晶体管和PMOS晶体管的多个SRAM单元10组成的存储单元阵列100A，以及连接到存储单元阵列的接地GND1或电源电压VDD1的偏置电路100B 100A。 偏置电路100B包括在沟道长度和沟道宽度以及沟道部分的掺杂剂和剂量方面与SRAM单元10的NMOS晶体管相同的NMOS晶体管121,122,133和134以及PMOS晶体管 111和112在沟道长度和沟道宽度方面与SRAM单元10的PMOS晶体管相同，并且就沟道部分的掺杂剂和剂量而言是相同的。 NMOS晶体管和PMOS晶体管的扩散区域形成在相同的半导体层中。

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