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公开(公告)号：US12080638B2
公开(公告)日：2024-09-03
申请号：US17816376
申请日：2022-07-29
发明人： Kuo-Chiang Ting , Chi-Hsi Wu , Shang-Yun Hou , Tu-Hao Yu , Chia-Hao Hsu , Pin-Tso Lin , Chia-Hsin Chen
IPC分类号： H01L23/498 , H01L21/683 , H01L21/56 , H01L23/00 , H01L23/31
CPC分类号： H01L23/49838 , H01L21/6835 , H01L23/49816 , H01L23/49894 , H01L21/563 , H01L21/565 , H01L23/3107 , H01L23/3128 , H01L23/3171 , H01L24/09 , H01L24/13 , H01L24/17 , H01L2221/68345 , H01L2221/68359 , H01L2224/13082 , H01L2224/13111 , H01L2224/13147 , H01L2224/17505 , H01L2924/3511
摘要： A semiconductor device includes a dielectric interposer, a first redistribution layer, a second redistribution layer and conductive structures. The conductive structures are through the dielectric interposer, wherein the conductive structures are electrically connected to the first redistribution layer and the second redistribution layer. Each of the conductive structures has a tapered profile. A width of each of the conductive structures proximal to the first redistribution layer is narrower than a width of each of the conductive structure proximal to the second redistribution layer.
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公开(公告)号：US12062590B2
公开(公告)日：2024-08-13
申请号：US16725189
申请日：2019-12-23
发明人： Ting-Yu Yeh , Chia-Hao Hsu , Weiming Chris Chen , Kuo-Chiang Ting , Tu-Hao Yu , Shang-Yun Hou
IPC分类号： H01L23/373 , H01L21/66 , H01L23/00 , H01L27/06
CPC分类号： H01L23/3735 , H01L22/32 , H01L23/562 , H01L24/17 , H01L27/0688 , H01L2924/3511 , H01L2924/3512
摘要： A semiconductor package structure includes a substrate, a first semiconductor and a second semiconductor over the substrate, and a multi-TIM structure disposed over the first semiconductor die and the second semiconductor die. The first semiconductor die includes a first heat output and the second semiconductor die includes a second heat output less than the first heat output. The multi-TIM structure includes a first TIM layer disposed over at least a portion of the first semiconductor die and a second TIM layer. A thermal conductivity of the first TIM layer is higher than a thermal conductivity of the second TIM layer. The first TIM layer covers the first semiconductor die.
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公开(公告)号：US20240088048A1
公开(公告)日：2024-03-14
申请号：US18152153
申请日：2023-01-10
发明人： Kuo-Chiang Ting , Jian-Wei Hong , Sung-Feng Yeh
IPC分类号： H01L23/538 , H01L21/48 , H01L23/00 , H01L23/31 , H01L25/065
CPC分类号： H01L23/5383 , H01L21/4853 , H01L21/4857 , H01L23/3121 , H01L23/5386 , H01L24/05 , H01L24/08 , H01L24/80 , H01L25/0652 , H01L25/0655 , H01L24/06 , H01L24/97 , H01L2224/0557 , H01L2224/05571 , H01L2224/05647 , H01L2224/06181 , H01L2224/08145 , H01L2224/08237 , H01L2224/80357 , H01L2224/80379 , H01L2224/80447 , H01L2224/97 , H01L2924/0504 , H01L2924/0544 , H01L2924/059
摘要： A chip structure provided herein includes a bridge structure including an interconnect bridge, a dielectric layer laterally surrounding the interconnect bridge and through dielectric vias extending from a top of the dielectric layer to a bottom of the dielectric layer, wherein a thickness of the interconnect bridge is identical to a height of each of the through dielectric vias; semiconductor dies disposed on the bridge structure, wherein each of the semiconductor dies overlaps both the interconnect bridge and the dielectric layer and is electrically connected to the interconnect bridge and at least one of the through dielectric vias; and a die support, the semiconductor dies being disposed between the die support and the bridge structure, wherein a sidewall of the die support is coplanar with a sidewall of the bridge structure.
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公开(公告)号：US20230386985A1
公开(公告)日：2023-11-30
申请号：US18359864
申请日：2023-07-26
发明人： Ting-Yu Yeh , Cing-He Chen , Kuo-Chiang Ting , Weiming Chris Chen , Chia-Hao Hsu , Kuan-Yu Huang , Shu-Chia Hsu
IPC分类号： H01L23/498 , H01L21/48 , H01L25/065
CPC分类号： H01L23/49816 , H01L21/4853 , H01L21/4857 , H01L21/486 , H01L23/49822 , H01L23/49833 , H01L23/49838 , H01L25/0655
摘要： A semiconductor structure includes a solder resist layer disposed on a circuit substrate and partially covering contact pads of the circuit substrate, and external terminals disposed on the solder resist layer and extending through the solder resist layer to land on the contact pads. The external terminals include a first external terminal and a second external terminal which have different heights. A first interface between the first external terminal and corresponding one of the contact pads underlying the first external terminal is less than a second interface between the second external terminal and another corresponding one of the contact pads underlying the second external terminal.
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公开(公告)号：US10978352B2
公开(公告)日：2021-04-13
申请号：US16728098
申请日：2019-12-27
IPC分类号： H01L21/8234 , H01L21/8238 , H01L21/84 , H01L27/088 , H01L29/66 , H01L21/762 , H01L27/092
摘要： In an embodiment, a FinFET device includes a semiconductor substrate and forming fins of a first height and a second height. A dielectric layer extends a fin of the first height to the fin of a second height. The dielectric layer is disposed on the top surface of the fin of the second height.
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公开(公告)号：US20200035690A1
公开(公告)日：2020-01-30
申请号：US16591816
申请日：2019-10-03
发明人： Fang Chen , Kuo-Chiang Ting , Jhon Jhy Liaw , Min-Chang Liang
IPC分类号： H01L27/11 , H01L27/11582 , H01L49/02 , H01L21/8238 , H01L23/522 , H01L23/528 , H01L27/088
摘要： An embodiment is an integrated circuit structure including a static random access memory (SRAM) cell having a first number of semiconductor fins, the SRAM cell having a first boundary and a second boundary parallel to each other, and a third boundary and a fourth boundary parallel to each other, the SRAM cell having a first cell height as measured from the third boundary to the fourth boundary, and a logic cell having the first number of semiconductor fins and the first cell height.
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公开(公告)号：US12033898B2
公开(公告)日：2024-07-09
申请号：US17301712
申请日：2021-04-12
IPC分类号： H01L21/84 , H01L21/762 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L27/092 , H01L29/66
CPC分类号： H01L21/823481 , H01L21/76224 , H01L21/76229 , H01L21/76232 , H01L21/823431 , H01L21/823821 , H01L21/823878 , H01L21/845 , H01L27/0886 , H01L27/0924 , H01L29/6681
摘要： In an embodiment, a method for fabricating a FinFET device includes providing a semiconductor substrate, etching the semiconductor substrate to form dummy fins and active fins. The group of dummy fins is etched through a patterned mask layer. An isolation feature is formed on the semiconductor substrate after etching the first group of dummy fins.
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公开(公告)号：US20210225666A1
公开(公告)日：2021-07-22
申请号：US16745610
申请日：2020-01-17
发明人： Shih Ting Lin , Szu-Wei Lu , Weiming Chris Chen , Kuo-Chiang Ting , Shang-Yun Hou , Chi-Hsi Wu
IPC分类号： H01L21/56 , H01L21/48 , H01L21/768
摘要： A method includes attaching semiconductor devices to an interposer structure, attaching the interposer structure to a first carrier substrate, attaching integrated passive devices to the first carrier substrate, forming an encapsulant over the semiconductor devices and the integrated passive devices, debonding the first carrier substrate, attaching the encapsulant and the semiconductor devices to a second carrier substrate, forming a first redistribution structure on the encapsulant, the interposer structure, and the integrated passive devices, wherein the first redistribution structure contacts the interposer structure and the integrated passive devices, and forming external connectors on the first redistribution structure.
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公开(公告)号：US10746923B2
公开(公告)日：2020-08-18
申请号：US16450725
申请日：2019-06-24
发明人： Chen-Hua Yu , Hsing-Kuo Hsia , Kuo-Chiang Ting , Pin-Tso Lin , Sung-Hui Huang , Shang-Yun Hou , Chi-Hsi Wu
摘要： A method includes forming silicon waveguide sections in a first oxide layer over a substrate, the first oxide layer disposed on the substrate, forming a routing structure over the first oxide layer, the routing structure including one or more insulating layers and one or more conductive features in the one or more insulating layers, recessing regions of the routing structure, forming nitride waveguide sections in the recessed regions of the routing structure, wherein the nitride waveguide sections extend over the silicon waveguide sections, forming a second oxide layer over the nitride waveguide sections, and attaching semiconductor dies to the routing structure, the dies electrically connected to the conductive features.
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公开(公告)号：US10468418B2
公开(公告)日：2019-11-05
申请号：US16051199
申请日：2018-07-31
发明人： Fang Chen , Kuo-Chiang Ting , Jhon Jhy Liaw , Min-Chang Liang
IPC分类号： H01L27/11 , H01L49/02 , H01L23/528 , H01L27/11582 , H01L21/8238 , H01L23/522 , H01L27/088
摘要： An embodiment is an integrated circuit structure including a static random access memory (SRAM) cell having a first number of semiconductor fins, the SRAM cell having a first boundary and a second boundary parallel to each other, and a third boundary and a fourth boundary parallel to each other, the SRAM cell having a first cell height as measured from the third boundary to the fourth boundary, and a logic cell having the first number of semiconductor fins and the first cell height.
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