公开(公告)号：US12033898B2

公开(公告)日：2024-07-09

申请号：US17301712

申请日：2021-04-12

Applicant: Taiwan Semiconductor Manufacturing Company., Ltd.

Inventor： Joanna Chaw Yane Yin ,  Chi-Hsi Wu ,  Kuo-Chiang Ting ,  Kuang-Hsin Chen

IPC: H01L21/84 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/66

CPC classification number: H01L21/823481 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/6681

Abstract: In an embodiment, a method for fabricating a FinFET device includes providing a semiconductor substrate, etching the semiconductor substrate to form dummy fins and active fins. The group of dummy fins is etched through a patterned mask layer. An isolation feature is formed on the semiconductor substrate after etching the first group of dummy fins.

公开(公告)号：US20210225666A1

公开(公告)日：2021-07-22

申请号：US16745610

申请日：2020-01-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih Ting Lin ,  Szu-Wei Lu ,  Weiming Chris Chen ,  Kuo-Chiang Ting ,  Shang-Yun Hou ,  Chi-Hsi Wu

IPC: H01L21/56 ,  H01L21/48 ,  H01L21/768

Abstract: A method includes attaching semiconductor devices to an interposer structure, attaching the interposer structure to a first carrier substrate, attaching integrated passive devices to the first carrier substrate, forming an encapsulant over the semiconductor devices and the integrated passive devices, debonding the first carrier substrate, attaching the encapsulant and the semiconductor devices to a second carrier substrate, forming a first redistribution structure on the encapsulant, the interposer structure, and the integrated passive devices, wherein the first redistribution structure contacts the interposer structure and the integrated passive devices, and forming external connectors on the first redistribution structure.

公开(公告)号：US10746923B2

公开(公告)日：2020-08-18

申请号：US16450725

申请日：2019-06-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Hua Yu ,  Hsing-Kuo Hsia ,  Kuo-Chiang Ting ,  Pin-Tso Lin ,  Sung-Hui Huang ,  Shang-Yun Hou ,  Chi-Hsi Wu

IPC: G02B6/12 ,  G02B6/124 ,  G02B6/136 ,  G02B6/122

Abstract: A method includes forming silicon waveguide sections in a first oxide layer over a substrate, the first oxide layer disposed on the substrate, forming a routing structure over the first oxide layer, the routing structure including one or more insulating layers and one or more conductive features in the one or more insulating layers, recessing regions of the routing structure, forming nitride waveguide sections in the recessed regions of the routing structure, wherein the nitride waveguide sections extend over the silicon waveguide sections, forming a second oxide layer over the nitride waveguide sections, and attaching semiconductor dies to the routing structure, the dies electrically connected to the conductive features.

公开(公告)号：US10468418B2

公开(公告)日：2019-11-05

申请号：US16051199

申请日：2018-07-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Fang Chen ,  Kuo-Chiang Ting ,  Jhon Jhy Liaw ,  Min-Chang Liang

IPC: H01L27/11 ,  H01L49/02 ,  H01L23/528 ,  H01L27/11582 ,  H01L21/8238 ,  H01L23/522 ,  H01L27/088

Abstract: An embodiment is an integrated circuit structure including a static random access memory (SRAM) cell having a first number of semiconductor fins, the SRAM cell having a first boundary and a second boundary parallel to each other, and a third boundary and a fourth boundary parallel to each other, the SRAM cell having a first cell height as measured from the third boundary to the fourth boundary, and a logic cell having the first number of semiconductor fins and the first cell height.

公开(公告)号：US10304800B2

公开(公告)日：2019-05-28

申请号：US15800962

申请日：2017-11-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Weiming Chris Chen ,  Ting-Yu Yeh ,  Chia-Hsin Chen ,  Tu-Hao Yu ,  Kuo-Chiang Ting ,  Shang-Yun Hou ,  Chi-Hsi Wu

IPC: H01L23/02 ,  H01L21/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00 ,  H01L23/498 ,  H01L25/16

Abstract: A semiconductor structure includes a first substrate including a first surface and a second surface opposite to the first surface; a first die disposed over the second surface of the first substrate; a plurality of first conductive bumps disposed between the first die and the first substrate; a molding disposed over the first substrate and surrounding the first die and the plurality of first conductive bumps; a second substrate disposed below the first surface of the first substrate; a plurality of second conductive bumps disposed between the first substrate and the second substrate; and a second die disposed between the first substrate and the second substrate.

公开(公告)号：US20190148329A1

公开(公告)日：2019-05-16

申请号：US15813538

申请日：2017-11-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo-Chiang Ting ,  Chi-Hsi Wu ,  Shang-Yun Hou ,  Tu-Hao Yu ,  Chia-Hao Hsu ,  Ting-Yu Yeh

IPC: H01L23/00 ,  H01L23/538 ,  H01L21/48 ,  H01L23/498 ,  H01L25/18 ,  H01L25/00

Abstract: A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.

公开(公告)号：US20180337189A1

公开(公告)日：2018-11-22

申请号：US16051199

申请日：2018-07-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Fang Chen ,  Kuo-Chiang Ting ,  Jhon Jhy Liaw ,  Min-Chang Liang

IPC: H01L27/11 ,  H01L49/02 ,  H01L27/11582 ,  H01L21/8238 ,  H01L23/528 ,  H01L23/522 ,  H01L27/088

CPC classification number: H01L27/1104 ,  H01L21/823821 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0886 ,  H01L27/1116 ,  H01L27/11582 ,  H01L28/00

Abstract: An embodiment is an integrated circuit structure including a static random access memory (SRAM) cell having a first number of semiconductor fins, the SRAM cell having a first boundary and a second boundary parallel to each other, and a third boundary and a fourth boundary parallel to each other, the SRAM cell having a first cell height as measured from the third boundary to the fourth boundary, and a logic cell having the first number of semiconductor fins and the first cell height.

公开(公告)号：US20180012809A1

公开(公告)日：2018-01-11

申请号：US15638589

申请日：2017-06-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Joanna Chaw Yane Yin ,  Chi-Hsi Wu ,  Kuo-Chiang Ting ,  Kuang-Hsin Chen

IPC: H01L21/8234 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/088

CPC classification number: H01L21/823481 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/6681

Abstract: The present disclosure provides many different embodiments of a FinFET device that provide one or more improvements over the prior art. In one embodiment, a FinFET includes a semiconductor substrate and a plurality of fins having a first height and a plurality of fin having a second height on the semiconductor substrate. The second height may be less than the first height.

公开(公告)号：US20170098582A1

公开(公告)日：2017-04-06

申请号：US15380376

申请日：2016-12-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Joanna Chaw Yane Yin ,  Chi-Hsi Wu ,  Kuo-Chiang Ting ,  Chen Kuang-Hsin

IPC: H01L21/8234 ,  H01L27/092 ,  H01L27/088 ,  H01L21/762 ,  H01L21/8238

CPC classification number: H01L21/823481 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/6681

Abstract: The present disclosure provides many different embodiments of a FinFET device that provide one or more improvements over the prior art. In one embodiment, a FinFET includes a semiconductor substrate and a plurality of fins having a first height and a plurality of fin having a second height on the semiconductor substrate. The second height may be less than the first height.

公开(公告)号：US12080638B2

公开(公告)日：2024-09-03

申请号：US17816376

申请日：2022-07-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Kuo-Chiang Ting ,  Chi-Hsi Wu ,  Shang-Yun Hou ,  Tu-Hao Yu ,  Chia-Hao Hsu ,  Pin-Tso Lin ,  Chia-Hsin Chen

IPC: H01L23/498 ,  H01L21/683 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49894 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/3171 ,  H01L24/09 ,  H01L24/13 ,  H01L24/17 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/17505 ,  H01L2924/3511

Abstract: A semiconductor device includes a dielectric interposer, a first redistribution layer, a second redistribution layer and conductive structures. The conductive structures are through the dielectric interposer, wherein the conductive structures are electrically connected to the first redistribution layer and the second redistribution layer. Each of the conductive structures has a tapered profile. A width of each of the conductive structures proximal to the first redistribution layer is narrower than a width of each of the conductive structure proximal to the second redistribution layer.