公开(公告)号：US12033898B2

公开(公告)日：2024-07-09

申请号：US17301712

申请日：2021-04-12

Applicant: Taiwan Semiconductor Manufacturing Company., Ltd.

Inventor： Joanna Chaw Yane Yin ,  Chi-Hsi Wu ,  Kuo-Chiang Ting ,  Kuang-Hsin Chen

IPC: H01L21/84 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/66

CPC classification number: H01L21/823481 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/6681

Abstract: In an embodiment, a method for fabricating a FinFET device includes providing a semiconductor substrate, etching the semiconductor substrate to form dummy fins and active fins. The group of dummy fins is etched through a patterned mask layer. An isolation feature is formed on the semiconductor substrate after etching the first group of dummy fins.

公开(公告)号：US10205024B2

公开(公告)日：2019-02-12

申请号：US15017225

申请日：2016-02-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chih-Chang Cheng ,  Fu-Yu Chu ,  Ruey-Hsin Liu ,  Kuang-Hsin Chen ,  Chih-Hsin Ko ,  Shih-Fen Huang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a gate structure formed over the substrate; a source region and a drain region formed in the substrate on either side of the gate structure, the source region and the drain region both having a first type of conductivity; and a field plate formed over the substrate between the gate structure and the drain region; wherein the field plate is coupled to the source region or a bulk electrode of the substrate. An associated method for fabricating the semiconductor structure is also disclosed.

公开(公告)号：US20180012809A1

公开(公告)日：2018-01-11

申请号：US15638589

申请日：2017-06-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Joanna Chaw Yane Yin ,  Chi-Hsi Wu ,  Kuo-Chiang Ting ,  Kuang-Hsin Chen

IPC: H01L21/8234 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/088

CPC classification number: H01L21/823481 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/6681

Abstract: The present disclosure provides many different embodiments of a FinFET device that provide one or more improvements over the prior art. In one embodiment, a FinFET includes a semiconductor substrate and a plurality of fins having a first height and a plurality of fin having a second height on the semiconductor substrate. The second height may be less than the first height.

公开(公告)号：US09716034B2

公开(公告)日：2017-07-25

申请号：US14918316

申请日：2015-10-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Bor-Zen Tien ,  Jhu-Ming Song ,  Hsuan-Han Lin ,  Kuang-Hsin Chen ,  Mu-Yi Lin ,  Tzong-Sheng Chang

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/00 ,  H01L21/285 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311

CPC classification number: H01L21/76849 ,  H01L21/02271 ,  H01L21/28008 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/31116 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76877 ,  H01L23/53228 ,  H01L23/53238 ,  H01L24/00 ,  H01L24/03 ,  H01L24/05 ,  H01L2221/1015 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0361 ,  H01L2224/05027 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05559 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/013 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/13091

Abstract: A method comprises forming a plurality of interconnect components over a gate structure, wherein a bottom metal line of the interconnect components is connected to the gate structure through a gate plug, depositing a dielectric layer over a top metal line of the interconnect components, forming an opening in the dielectric layer, depositing a first barrier layer on a bottom and sidewalls of the opening using a non-plasma based deposition process, depositing a second barrier layer over the first barrier layer using a plasma based deposition process and forming a pad in the opening.

公开(公告)号：US20140246709A1

公开(公告)日：2014-09-04

申请号：US13782072

申请日：2013-03-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Sheng-Ching Chen ,  Kuang-Hsin Chen ,  Bor-Zen Tien ,  Tzong-Sheng Chang

IPC: H01L29/78 ,  H01L21/76

CPC classification number: H01L29/78 ,  H01L21/76 ,  H01L29/66545

Abstract: A semiconductor device includes a gate structure over a substrate. The device further includes an isolation feature in the substrate and adjacent to an edge of the gate structure. The device also includes a spacer overlying a sidewall of the gate structure. The spacer has a bottom lower than a top surface of the substrate.

Abstract translation: 半导体器件包括在衬底上的栅极结构。 该器件还包括衬底中的隔离特征并且与栅极结构的边缘相邻。 该装置还包括覆盖栅极结构的侧壁的间隔物。 间隔物的底部低于衬底的顶表面。

公开(公告)号：US11158739B2

公开(公告)日：2021-10-26

申请号：US16273486

申请日：2019-02-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chih-Chang Cheng ,  Fu-Yu Chu ,  Ruey-Hsin Liu ,  Kuang-Hsin Chen ,  Chih-Hsin Ko ,  Shih-Fen Huang

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/417

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a gate structure formed over the substrate; a source region and a drain region formed in the substrate on either side of the gate structure, the source region and the drain region both having a first type of conductivity; and a field plate formed over the substrate between the gate structure and the drain region; wherein the field plate is coupled to the source region or a bulk electrode of the substrate. An associated method for fabricating the semiconductor structure is also disclosed.

公开(公告)号：US11011419B2

公开(公告)日：2021-05-18

申请号：US16831313

申请日：2020-03-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Bor-Zen Tien ,  Jhu-Ming Song ,  Hsuan-Han Lin ,  Kuang-Hsin Chen ,  Mu-Yi Lin ,  Tzong-Sheng Chang

IPC: H01L21/768 ,  H01L21/285 ,  H01L23/00 ,  H01L23/532 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311

Abstract: An apparatus includes a plurality of interconnect structures over a substrate, a dielectric layer formed over a top metal line of the plurality of interconnect structures, a first barrier layer on a bottom and sidewalls of an opening in the dielectric layer, wherein the first barrier layer is formed of a first material and has a first thickness, a second barrier layer over the first barrier layer, wherein the second barrier layer is formed of a second material different from the first material and has a second thickness and a pad over the second barrier layer, wherein the pad is formed of a third material.

公开(公告)号：US20180337248A1

公开(公告)日：2018-11-22

申请号：US16050250

申请日：2018-07-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： I-Chen Huang ,  Yi-Ju Hsu ,  Chi-Wen Liu ,  Kuang-Hsin Chen ,  Yung-Hsien Wu ,  Chin-Yu Chen

IPC: H01L29/51 ,  H01L21/28 ,  H01L21/02

CPC classification number: H01L29/513 ,  H01L21/02181 ,  H01L21/02194 ,  H01L21/02255 ,  H01L21/02304 ,  H01L21/0234 ,  H01L21/28158 ,  H01L21/28185 ,  H01L21/28194 ,  H01L29/517 ,  H01L29/785

Abstract: A semiconductor device and method of manufacturing same are described. A first hafnium oxide (HfO2) layer is formed on a substrate. A titanium (Ti) layer is formed over the first hafnium oxide layer. A second hafnium oxide layer is formed over the titanium layer. The composite device structure is thermally annealed to produce a high-k dielectric structure having a hafnium titanium oxide (HfxTi1-xO2) layer interposed between the first hafnium oxide layer and the second hafnium oxide layer.

公开(公告)号：US20180337123A1

公开(公告)日：2018-11-22

申请号：US16047048

申请日：2018-07-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Cheng-Chieh Lai ,  Meng-Ting Yu ,  Yung-Hsien Wu ,  Kuang-Hsin Chen

IPC: H01L23/522 ,  H01L49/02 ,  H01L27/108 ,  H01L21/283 ,  H01L21/02 ,  H01L27/06 ,  H01L23/535 ,  H01L21/324

CPC classification number: H01L23/5223 ,  H01L21/02532 ,  H01L21/02601 ,  H01L21/283 ,  H01L21/324 ,  H01L23/535 ,  H01L27/0629 ,  H01L27/10814 ,  H01L28/40 ,  H01L28/60

Abstract: The present disclosure provides one embodiment of a semiconductor structure that includes an interconnection structure formed on a semiconductor substrate; and a capacitor disposed in the interconnection structure. The interconnection structure includes a top electrode; a bottom electrode; a dielectric material layer sandwiched between the top and bottom electrodes; and a nanocrystal layer embedded in the dielectric material layer.

公开(公告)号：US20170200673A1

公开(公告)日：2017-07-13

申请号：US14995036

申请日：2016-01-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Cheng-Chieh Lai ,  Meng-Ting Yu ,  Yung-Hsien Wu ,  Kuang-Hsin Chen

IPC: H01L23/522 ,  H01L21/283 ,  H01L49/02 ,  H01L21/02 ,  H01L23/535 ,  H01L27/06 ,  H01L21/324

CPC classification number: H01L23/5223 ,  H01L21/02532 ,  H01L21/02601 ,  H01L21/283 ,  H01L21/324 ,  H01L23/535 ,  H01L27/0629 ,  H01L27/10814 ,  H01L28/40 ,  H01L28/60

Abstract: The present disclosure provides one embodiment of a semiconductor structure that includes an interconnection structure formed on a semiconductor substrate; and a capacitor disposed in the interconnection structure. The interconnection structure includes a top electrode; a bottom electrode; a dielectric material layer sandwiched between the top and bottom electrodes; and a nanocrystal layer embedded in the dielectric material layer.