公开(公告)号：US11011419B2

公开(公告)日：2021-05-18

申请号：US16831313

申请日：2020-03-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Bor-Zen Tien ,  Jhu-Ming Song ,  Hsuan-Han Lin ,  Kuang-Hsin Chen ,  Mu-Yi Lin ,  Tzong-Sheng Chang

IPC: H01L21/768 ,  H01L21/285 ,  H01L23/00 ,  H01L23/532 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311

Abstract: An apparatus includes a plurality of interconnect structures over a substrate, a dielectric layer formed over a top metal line of the plurality of interconnect structures, a first barrier layer on a bottom and sidewalls of an opening in the dielectric layer, wherein the first barrier layer is formed of a first material and has a first thickness, a second barrier layer over the first barrier layer, wherein the second barrier layer is formed of a second material different from the first material and has a second thickness and a pad over the second barrier layer, wherein the pad is formed of a third material.

公开(公告)号：US09508590B2

公开(公告)日：2016-11-29

申请号：US14996951

申请日：2016-01-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tsung-Yu Chiang ,  Kuang-Hsin Chen ,  Bor-Zen Tien ,  Tzong-Sheng Chang

IPC: H01L21/768 ,  H01L29/78 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L21/3213 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L21/76805 ,  H01L21/28088 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/76877 ,  H01L29/0649 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/66568 ,  H01L29/78

Abstract: In some embodiments, a method of manufacturing a device includes providing a first device with an isolation area, an active area next to the isolation area, a metal gate above the isolation area and the active area, and a dielectric layer above the metal gate. The method also includes forming a first opening within a conductive layer of the metal gate, and a second opening within the dielectric layer. The first opening and the second opening are connected, and are of a first shape. The method further includes expanding the first opening to form a third opening of a second shape within the conductive layer of the metal gate and beneath the dielectric layer, forming a first contact part by filling the third opening, and forming a second contact part by filling the second opening, the first contact part being connected to the second contact part.

Abstract translation: 在一些实施例中，一种制造器件的方法包括：提供具有隔离区域的第一器件，隔离区域旁边的有源区域，隔离区域上方的金属栅极和有源区域以及金属栅极上方的电介质层。 该方法还包括在金属栅极的导电层内形成第一开口，以及在电介质层内形成第二开口。 第一开口和第二开口连接，并且是第一形状。 该方法还包括扩展第一开口以在金属栅极的导电层内和电介质层之下形成第二形状的第三开口，通过填充第三开口形成第一接触部分，并通过填充形成第二接触部分 所述第二开口，所述第一接触部分连接到所述第二接触部分。

公开(公告)号：US09716034B2

公开(公告)日：2017-07-25

申请号：US14918316

申请日：2015-10-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Bor-Zen Tien ,  Jhu-Ming Song ,  Hsuan-Han Lin ,  Kuang-Hsin Chen ,  Mu-Yi Lin ,  Tzong-Sheng Chang

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/00 ,  H01L21/285 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311

CPC classification number: H01L21/76849 ,  H01L21/02271 ,  H01L21/28008 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/31116 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76877 ,  H01L23/53228 ,  H01L23/53238 ,  H01L24/00 ,  H01L24/03 ,  H01L24/05 ,  H01L2221/1015 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0361 ,  H01L2224/05027 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05559 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/013 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/13091

Abstract: A method comprises forming a plurality of interconnect components over a gate structure, wherein a bottom metal line of the interconnect components is connected to the gate structure through a gate plug, depositing a dielectric layer over a top metal line of the interconnect components, forming an opening in the dielectric layer, depositing a first barrier layer on a bottom and sidewalls of the opening using a non-plasma based deposition process, depositing a second barrier layer over the first barrier layer using a plasma based deposition process and forming a pad in the opening.

公开(公告)号：US20140246709A1

公开(公告)日：2014-09-04

申请号：US13782072

申请日：2013-03-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Sheng-Ching Chen ,  Kuang-Hsin Chen ,  Bor-Zen Tien ,  Tzong-Sheng Chang

IPC: H01L29/78 ,  H01L21/76

CPC classification number: H01L29/78 ,  H01L21/76 ,  H01L29/66545

Abstract: A semiconductor device includes a gate structure over a substrate. The device further includes an isolation feature in the substrate and adjacent to an edge of the gate structure. The device also includes a spacer overlying a sidewall of the gate structure. The spacer has a bottom lower than a top surface of the substrate.

Abstract translation: 半导体器件包括在衬底上的栅极结构。 该器件还包括衬底中的隔离特征并且与栅极结构的边缘相邻。 该装置还包括覆盖栅极结构的侧壁的间隔物。 间隔物的底部低于衬底的顶表面。

公开(公告)号：US20200227316A1

公开(公告)日：2020-07-16

申请号：US16831313

申请日：2020-03-26

Applicant: Taiwan Semiconductor Manufacturing Company Ltd.

Inventor： Bor-Zen Tien ,  Jhu-Ming Song ,  Hsuan-Han Lin ,  Kuang-Hsin Chen ,  Mu-Yi Lin ,  Tzong-Sheng Chang

IPC: H01L21/768 ,  H01L21/285 ,  H01L23/00 ,  H01L23/532 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311

Abstract: An apparatus includes a plurality of interconnect structures over a substrate, a dielectric layer formed over a top metal line of the plurality of interconnect structures, a first barrier layer on a bottom and sidewalls of an opening in the dielectric layer, wherein the first barrier layer is formed of a first material and has a first thickness, a second barrier layer over the first barrier layer, wherein the second barrier layer is formed of a second material different from the first material and has a second thickness and a pad over the second barrier layer, wherein the pad is formed of a third material.

公开(公告)号：US20140252621A1

公开(公告)日：2014-09-11

申请号：US13791076

申请日：2013-03-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hsuan-Han Lin ,  Jhu-Ming Song ,  Mu-Yi Lin ,  Kuang-Hsin Chen ,  Bor-Zen Tien ,  Tzong-Sheng Chang

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76849 ,  H01L21/02271 ,  H01L21/28008 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/31116 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76877 ,  H01L23/53228 ,  H01L23/53238 ,  H01L24/00 ,  H01L24/03 ,  H01L24/05 ,  H01L2221/1015 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0361 ,  H01L2224/05027 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05559 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/013 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/13091

Abstract: A method for forming interconnect structures comprises forming a metal line made of a first conductive material over a substrate, depositing a dielectric layer over the metal line, patterning the dielectric layer to form an opening, depositing a first barrier layer on a bottom and sidewalls of the opening using an atomic layer deposition technique, depositing a second barrier layer over the first barrier layer, wherein the first barrier layer is coupled to ground and forming a pad made of a second conductive material in the opening.

Abstract translation: 用于形成互连结构的方法包括在衬底上形成由第一导电材料制成的金属线，在金属线上方沉积电介质层，图案化介电层以形成开口，在第一阻挡层的底部和侧壁上沉积第一阻挡层 所述开口使用原子层沉积技术，在所述第一阻挡层上沉积第二阻挡层，其中所述第一阻挡层耦合到地面并形成由所述开口中的第二导电材料制成的焊盘。

公开(公告)号：US20160133509A1

公开(公告)日：2016-05-12

申请号：US14996951

申请日：2016-01-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tsung-Yu Chiang ,  Kuang-Hsin Chen ,  Bor-Zen Tien ,  Tzong-Sheng Chang

IPC: H01L21/768 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/28 ,  H01L29/06

CPC classification number: H01L21/76805 ,  H01L21/28088 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/76877 ,  H01L29/0649 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/66568 ,  H01L29/78

Abstract: In some embodiments, a method of manufacturing a device includes providing a first device with an isolation area, an active area next to the isolation area, a metal gate above the isolation area and the active area, and a dielectric layer above the metal gate. The method also includes forming a first opening within a conductive layer of the metal gate, and a second opening within the dielectric layer. The first opening and the second opening are connected, and are of a first shape. The method further includes expanding the first opening to form a third opening of a second shape within the conductive layer of the metal gate and beneath the dielectric layer, forming a first contact part by filling the third opening, and forming a second contact part by filling the second opening, the first contact part being connected to the second contact part.

Abstract translation: 在一些实施例中，一种制造器件的方法包括：提供具有隔离区域的第一器件，隔离区域旁边的有源区域，隔离区域上方的金属栅极和有源区域以及金属栅极上方的电介质层。 该方法还包括在金属栅极的导电层内形成第一开口，以及在电介质层内形成第二开口。 第一开口和第二开口连接，并且是第一形状。 该方法还包括扩展第一开口以在金属栅极的导电层内和电介质层之下形成第二形状的第三开口，通过填充第三开口形成第一接触部分，并通过填充形成第二接触部分 所述第二开口，所述第一接触部分连接到所述第二接触部分。

公开(公告)号：US09190319B2

公开(公告)日：2015-11-17

申请号：US13791076

申请日：2013-03-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsuan-Han Lin ,  Jhu-Ming Song ,  Mu-Yi Lin ,  Kuang-Hsin Chen ,  Bor-Zen Tien ,  Tzong-Sheng Chang

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/00 ,  H01L21/285

CPC classification number: H01L21/76849 ,  H01L21/02271 ,  H01L21/28008 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/31116 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76877 ,  H01L23/53228 ,  H01L23/53238 ,  H01L24/00 ,  H01L24/03 ,  H01L24/05 ,  H01L2221/1015 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0361 ,  H01L2224/05027 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05559 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/013 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/13091

Abstract: A method for forming interconnect structures comprises forming a metal line made of a first conductive material over a substrate, depositing a dielectric layer over the metal line, patterning the dielectric layer to form an opening, depositing a first barrier layer on a bottom and sidewalls of the opening using an atomic layer deposition technique, depositing a second barrier layer over the first barrier layer, wherein the first barrier layer is coupled to ground and forming a pad made of a second conductive material in the opening.

Abstract translation: 用于形成互连结构的方法包括在衬底上形成由第一导电材料制成的金属线，在金属线上方沉积电介质层，图案化介电层以形成开口，在第一阻挡层的底部和侧壁上沉积第一阻挡层 所述开口使用原子层沉积技术，在所述第一阻挡层上沉积第二阻挡层，其中所述第一阻挡层耦合到地面并形成由所述开口中的第二导电材料制成的焊盘。

公开(公告)号：US08860151B2

公开(公告)日：2014-10-14

申请号：US13782072

申请日：2013-03-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sheng-Ching Chen ,  Kuang-Hsin Chen ,  Bor-Zen Tien ,  Tzong-Sheng Chang

IPC: H01L21/02 ,  H01L29/78 ,  H01L21/76

CPC classification number: H01L29/78 ,  H01L21/76 ,  H01L29/66545

Abstract: A semiconductor device includes a gate structure over a substrate. The device further includes an isolation feature in the substrate and adjacent to an edge of the gate structure. The device also includes a spacer overlying a sidewall of the gate structure. The spacer has a bottom lower than a top surface of the substrate.

Abstract translation: 半导体器件包括在衬底上的栅极结构。 该器件还包括衬底中的隔离特征并且与栅极结构的边缘相邻。 该装置还包括覆盖栅极结构的侧壁的间隔物。 间隔物的底部低于衬底的顶表面。

公开(公告)号：US20170323827A1

公开(公告)日：2017-11-09

申请号：US15657828

申请日：2017-07-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Bor-Zen Tien ,  Jhu-Ming Song ,  Hsuan-Han Lin ,  Kuang-Hsin Chen ,  Mu-Yi Lin ,  Tzong-Sheng Chang

IPC: H01L21/768 ,  H01L21/285 ,  H01L23/00 ,  H01L21/311 ,  H01L21/02 ,  H01L23/532 ,  H01L21/28

CPC classification number: H01L21/76849 ,  H01L21/02271 ,  H01L21/28008 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/31116 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76877 ,  H01L23/53228 ,  H01L23/53238 ,  H01L24/00 ,  H01L24/03 ,  H01L24/05 ,  H01L2221/1015 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0361 ,  H01L2224/05027 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05559 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/013 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/13091

Abstract: An apparatus includes a plurality of interconnect structures over a substrate, a dielectric layer formed over a top metal line of the plurality of interconnect structures, a first barrier layer on a bottom and sidewalls of an opening in the dielectric layer, wherein the first barrier layer is formed of a first material and has a first thickness, a second barrier layer over the first barrier layer, wherein the second barrier layer is formed of a second material different from the first material and has a second thickness and a pad over the second barrier layer, wherein the pad is formed of a third material.